公开(公告)号：US20070144772A1

公开(公告)日：2007-06-28

申请号：US11641810

申请日：2006-12-20

Applicant: John Lauffer ,  James Larnerd ,  Voya Markovich

Inventor： John Lauffer ,  James Larnerd ,  Voya Markovich

IPC: H05K1/16

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.

Abstract translation: 一种制造电路化衬底的方法，其包括多个邻接的开放段，其限定导电层内的相对边缘部分以隔离导电层的分离部分，使得该层可用于不同的功能，例如电力和地面 元件，在包括基板作为其一部分的产品（例如，电气组件）内。 还提供了代表其中可以使用衬底的产品之一的信息处理系统，例如主机计算机。

公开(公告)号：US07187558B2

公开(公告)日：2007-03-06

申请号：US11245723

申请日：2005-10-06

Applicant: Scott T. Parkhill ,  Sayeed Ahmed ,  Fred Flett

Inventor： Scott T. Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC: H01R9/00

CPC classification number: H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H02M7/003 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K7/1432 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49009 ,  Y10T29/49117 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

公开(公告)号：US20050194675A1

公开(公告)日：2005-09-08

申请号：US11103939

申请日：2005-04-12

Applicant: Jennifer Hester ,  Yuan-Liang Li ,  Michael Desmith ,  David Figueroa ,  Dong Zhong

Inventor： Jennifer Hester ,  Yuan-Liang Li ,  Michael Desmith ,  David Figueroa ,  Dong Zhong

IPC: H01G4/38 ,  H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H05K1/11 ,  H01L23/48

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract translation: 根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及 设置在所述第一导电平面和所述第二导电平面之间的电介质。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。

公开(公告)号：US06937480B2

公开(公告)日：2005-08-30

申请号：US10142203

申请日：2002-05-10

Applicant: Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

Inventor： Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

IPC: H05K1/00 ,  H05K1/02 ,  H05K9/00 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/10689

Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.

Abstract translation: 提供了一种印刷电路板，其可以甚至应用于高速操作的电路板，并且可以抑制电磁波辐射，并且可以抑制安装密度的劣化。 在印刷电路板上层叠有第一信号线层，具有第一电源线的第一接地层，具有第二电源线的第二接地层和第二信号线层。 第一接地层和第二接地层通过许多通孔进行层间连接。 流过信号线的信号电流的返回电流在第一接地层中流动，并且在第一电源线的位置处，中途返回电流的路径被切断。 然而，返回电流被通孔旋转到第二接地层，并在那里流动。

公开(公告)号：US06900992B2

公开(公告)日：2005-05-31

申请号：US09955230

申请日：2001-09-18

Applicant: Christopher J. Kelly ,  Jeffrey L. Krieger ,  Raymond P. Askew

Inventor： Christopher J. Kelly ,  Jeffrey L. Krieger ,  Raymond P. Askew

IPC: H05K1/02 ,  H05K3/46 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0233 ,  H05K1/0237 ,  H05K1/0243 ,  H05K3/4644 ,  H05K2201/086 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

Abstract: A printed circuit board includes a signal layer and a supply voltage plane layer. The signal layer includes traces to communicate signals that are not associated with regulated supply voltages. The supply voltage plane is embedded in the signal layer to supply power to multiple supply voltage pins of a component that is mounted to the printed circuit board. The printed circuit board may also include a supply voltage plane layer to communicate a supply voltage. A ground plane may be embedded in the supply voltage plane layer to provide ground connections to multiple pins of the component.

Abstract translation: 印刷电路板包括信号层和电源电压平面层。 信号层包括用于传送与调节电源电压无关的信号的迹线。 电源电压平面嵌入在信号层中，为安装到印刷电路板的部件的多个电源电压引脚供电。 印刷电路板还可以包括用于传送电源电压的电源电压平面层。 接地平面可以嵌入在电源电压平面层中，以提供与组件的多个引脚的接地连接。

公开(公告)号：US06888071B2

公开(公告)日：2005-05-03

申请号：US10710731

申请日：2004-07-30

Applicant: Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

Inventor： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC: H05K1/00 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

Abstract translation: 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以被 相同的控制芯片。

公开(公告)号：US20040257780A1

公开(公告)日：2004-12-23

申请号：US10602096

申请日：2003-06-23

Inventor： Jennifer A. Hester ,  Yuan-Liang Li ,  Michael M. Desmith ,  David G. Figueroa ,  Dong Zhong

IPC: H05K007/06

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract translation: 根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及 设置在所述第一导电平面和所述第二导电平面之间的电介质。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。

公开(公告)号：US20020176236A1

公开(公告)日：2002-11-28

申请号：US10142203

申请日：2002-05-10

Applicant: FUJI XEROX CO., LTD.

Inventor： Daisuke Iguchi ,  Joji Wakita ,  Kazumi Ikeda ,  Osamu Ueno

IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/09254 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09618 ,  H05K2201/10689

Abstract: A printed wiring board is provided which can be applied even to circuit boards operating at high speed, and which can suppress electromagnetic wave radiation, and which can suppress a deterioration in density of mounting. At the printed wiring board, a first signal wire layer, a first ground layer having a first power source wire, a second ground layer having a second power source wire, and a second signal wire layer, are laminated. The first ground layer and the second ground layer are interlayer-connected by many via holes. Return current, of signal current flowing through a signal wire, flows in the first ground layer, and a path of the return current is cut midway therealong at a position of the first power source wire. However, the return current is detoured by the via hole to the second ground layer, and flows thereat.

Abstract translation: 提供了一种印刷电路板，其可以甚至应用于高速操作的电路板，并且可以抑制电磁波辐射，并且可以抑制安装密度的劣化。 在印刷电路板上层叠有第一信号线层，具有第一电源线的第一接地层，具有第二电源线的第二接地层和第二信号线层。 第一接地层和第二接地层通过许多通孔进行层间连接。 流过信号线的信号电流的返回电流在第一接地层中流动，并且在第一电源线的位置处，中途返回电流的路径被切断。 然而，返回电流被通孔旋转到第二接地层，并在那里流动。

公开(公告)号：US06477057B1

公开(公告)日：2002-11-05

申请号：US09640538

申请日：2000-08-17

Applicant: Patrick H. Buffet ,  Paul Lee Clouser ,  Danny Marvin Neal

Inventor： Patrick H. Buffet ,  Paul Lee Clouser ,  Danny Marvin Neal

IPC: H05K702

CPC classification number: H05K1/0216 ,  G06F1/189 ,  G06F1/26 ,  H05K1/0231 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A method and implementing computer system are provided in which de-coupling capacitors are used at driver and receiver sources, and defined gaps are created separating power and ground areas on a voltage reference plane of a circuit board. Short-circuit via connections are also provided through one or more vias between spatially separated circuit board layers. Each driver or receiver module includes the driver or receiver along with an associated gap, capacitor and via connections to VDD and ground planes, all included within a defined proximity to effectively block switching energy and/or VDD noise from entering the tri-plate ground-to-ground reference system. In a related exemplary construction, signal lines are placed at predetermined positions between ground planes to provide a tri-plate circuit board structure for transmitting logic signals from a driver to one or more receivers.

Abstract translation: 提供了一种方法和实现的计算机系统，其中在驱动器和接收器源处使用解耦电容器，并且在电路板的电压参考平面上分离电源和接地区域来创建限定的间隙。 通过连接的短路也通过空间分离的电路板层之间的一个或多个通孔提供。 每个驱动器或接收器模块包括驱动器或接收器以及相关联的间隙，电容器和到VDD和接地层的通孔连接，所有这些都包括在限定的接近度内，以有效地阻止开关能量和/或VDD噪声进入三板接地平面， 对地参考系统。 在相关的示例性结构中，信号线被放置在接地平面之间的预定位置处，以提供用于将逻辑信号从驾驶员发送到一个或多个接收器的三板电路板结构。

公开(公告)号：US20020060366A1

公开(公告)日：2002-05-23

申请号：US09817787

申请日：2001-03-27

Inventor： Atsushi Kikuchi ,  Makoto Iijima ,  Yoshihiko Ikemoto ,  Muneharu Morioka ,  Yoshiyuki Kimura

IPC: H01L023/48

CPC classification number: H05K1/0245 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09345 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multilayer wiring substrate comprises differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.

Abstract translation: 多层布线基板包括布置在第一电源平面和第一接地平面之间的第一绝缘层内的差分信号线; 以及放置在第二电源平面和第二接地平面之间的第二绝缘层内的一般信号线。 在多层布线基板中，差分信号线被放置在与具有每个通用信号线的平面不同的平面中，使得不同的平面包括具有差分信号线的第一区域，以及具有第二 电源平面和第二个接地层。 通常的信号线以叠层状态放置在第二区域的垂直方向上，使得每条通用信号线都位于第二电源平面和第二接地面之间。