Abstract:
The description relates to electronic prototyping platforms. One example can include an electrically insulative substrate having generally opposing first and second major surfaces and that includes an orientation feature that is visible on both of the first and second major surfaces. The example can include a first mounting hole through the substrate that is bordered by a first electrical conductor associated with data transmission. The example can also include a second mounting hole through the substrate that is bordered by a second electrical conductor associated with electrical ground, and a third mounting hole through the substrate that is bordered by a third electrical conductor associated with electrical power. The example can also include an edge connector tab defined by the substrate and having three exposed electrically conductive contacts that are coupled to the data electrical conductor, the ground electrical conductor, and the power electrical conductor and insulated from one another.
Abstract:
According to one embodiment, a printed circuit board includes a substrate and a shared pad group provided on the substrate and including a plurality of shared pads. The shared pads include a first area, a second area smaller in size than the first area, a port of which is overlap the first area and an other port of which is located to protrude from the first area to a side of another one of the shared pads, and a second side edge located on a side of another shared pad. The second pad side edge includes a first side edge defining the first area, a second side edge defining the second area and displaced on a side of another shared pad with respect to the first side edge, and a sloping side edge connecting the first side edge and the second side edge to each other.
Abstract:
An electronic device may include surface mount technology components mounted to a printed circuit board. The surface mount technology components may include electrical components such as resistors, inductors, and capacitors. In order to reduce the size of the electronic device, surface mount technology components may be stacked. A surface mount technology component may be mounted to metal members that electrically connect the surface mount technology component to contact pads on a printed circuit board. A surface mount technology component may be provided with integral standoff portions, and a second surface mount technology component may be mounted to the integral standoff portions. A single surface mount technology component may be used to implement different circuits depending on which face of the surface mount technology component is mounted to the printed circuit board.
Abstract:
A package comprises a body, and an electrically conductive pattern supported by said body. An interface portion is configured to receive a module to a removable attachment with the package. The electrically conductive pattern comprises, at least partly within said interface portion, a wireless coupling pattern that constitutes one half of a wireless coupling arrangement.
Abstract:
A package comprises a body, and an electrically conductive pattern supported by said body. An interface portion is configured to receive a module to a removable attachment with the package. The electrically conductive pattern comprises, at least partly within said interface portion, a wireless coupling pattern that constitutes one half of a wireless coupling arrangement.
Abstract:
Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be aligned and connected to two electrodes different from each other to solve a limitation in which a nano-scale LED device having a nano unit is coupled to two electrodes different from each other in a stand-up state. Also, since the LED device and the electrodes are disposed on the same plane, light extraction efficiency of the LED device may be improved. Furthermore, the number of nano-scale LED devices may be adjusted. Second, since the nano-scale LED device does not stand up to be three-dimensionally coupled to upper and lower electrodes, but lies to be coupled to two electrodes different from each other on the same plane, the light extraction efficiency may be very improved. Also, since a separate layer is formed on a surface of the LED device to prevent the LED device and the electrode from being electrically short-circuited, defects of the LED electrode assembly may be minimized. Also, in preparation for the occurrence of the very rare defects of the LED device, the plurality of LED devices may be connected to the electrode to maintain the original function of the nano-scale LED electrode assembly.
Abstract:
An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape.
Abstract:
An Integrated Circuit (IC) package comprises a package comprising a first set of pads having a pinout that is compatible with a chip core of a product family. A second set of pads are on substantially the same plane as the first set of pads and outside the package core. The second set of pads is configured to accommodate a circuit outside the chip core. The geometric center of the package core is different from the geometric center of the IC package.
Abstract:
A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes.
Abstract:
Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.