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    Semiconductor package, method of production of same, and semiconductor device
    111.
    发明申请
    Semiconductor package, method of production of same, and semiconductor device 有权
    半导体封装，其制造方法和半导体器件

    公开(公告)号：US20040041270A1

    公开(公告)日：2004-03-04

    申请号：US10647386

    申请日：2003-08-26

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

    IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

    CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

    Abstract: A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

    Abstract translation: 一种半导体封装，其具有多层互连结构，用于将半导体芯片安装在其顶表面上，其中所述多层互连结构的最上层堆叠结构包括电容器结构，所述电容器结构具有介电层，所述电介质层由混合电沉积层 高介电常数无机填料和绝缘树脂，并且包括用于直接连接具有半导体芯片电极的顶电极和底电极的芯片连接焊盘，从而可以确保互连图案设计的更大自由度，电容器和半导体芯片的接近程度 可以大大改善，并且可以使包装重量更小更轻，其制造方法以及使用该半导体封装的半导体器件。

    Thin film capacitor using conductive polymers
    112.
    发明申请
    Thin film capacitor using conductive polymers 失效
    使用导电聚合物的薄膜电容器

    公开(公告)号：US20030103319A1

    公开(公告)日：2003-06-05

    申请号：US10285748

    申请日：2002-11-01

    Inventor： Prabhat Kumar ,  Henning Uhlenhut

    IPC: H01G004/20

    CPC classification number: H01G9/15 ,  H01G4/10 ,  H01G11/48 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0329 ,  H05K2201/09763 ,  Y02E60/13

    Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film comprising an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film comprising an electrically conductive polymer located on the pentoxide layer.

    Abstract translation: 本发明涉及一种薄膜电容器，其包含（a）基底，（b）第一聚合物膜，其包含位于基底上的导电聚合物，（c）五氧化物层，其选自五氧化二钽或五氧化二铌 ，及其混合物，（d）包含位于五氧化物层上的导电聚合物的第二聚合物膜。

    Method of manufacturing non-linear resistive element array
    116.
    发明授权
    Method of manufacturing non-linear resistive element array 失效
    制造非线性电阻元件阵列的方法

    公开(公告)号：US4895789A

    公开(公告)日：1990-01-23

    申请号：US174833

    申请日：1988-03-29

    Applicant: Shunichi Motte ,  Mitsuya Suzuki

    Inventor： Shunichi Motte ,  Mitsuya Suzuki

    IPC: G02F1/1365 ,  H01C17/00 ,  H05K1/16 ,  H05K3/06 ,  H05K3/38

    CPC classification number: H05K1/167 ,  G02F1/1365 ,  H01C17/003 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K2203/1105 ,  H05K3/064 ,  H05K3/388

    Abstract: A method for manufacturing a non-linear resistive element array on a substrate, comprising: depositing a first conductive layer on the substrate and selectively forming the layer in a desired pattern; depositing a non-linear resistive layer on the first conductive layer; depositing a second conductive layer on the non-linear resistive layer; forming the second conductive layer in a desired pattern by etching process using a patterned resist layer as a mask; and forming the non-linear resistive layer in a desired pattern using the resist layer as a mask.

    Abstract translation: 一种用于在衬底上制造非线性电阻元件阵列的方法，包括：在所述衬底上沉积第一导电层并以期望的图案选择性地形成所述层; 在第一导电层上沉积非线性电阻层; 在所述非线性电阻层上沉积第二导电层; 通过使用图案化的抗蚀剂层作为掩模的蚀刻工艺以期望的图案形成第二导电层; 以及使用抗蚀剂层作为掩模，以期望的图案形成非线性电阻层。

    High-frequency circuit device with an annular capacitor on the back of an insulated substrate
    117.
    发明授权
    High-frequency circuit device with an annular capacitor on the back of an insulated substrate 失效
    高频电路器件在绝缘基板的背面具有环形电容器

    公开(公告)号：US4611882A

    公开(公告)日：1986-09-16

    申请号：US530237

    申请日：1983-09-08

    Applicant: Susumu Ushida

    Inventor： Susumu Ushida

    IPC: H01L23/52 ,  H01L23/66 ,  H01L25/16 ,  H01L27/13 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H01L39/02 ,  H01G1/005

    CPC classification number: H05K1/162 ,  H01L23/66 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/112 ,  H05K2201/09763 ,  H05K3/42

    Abstract: A high-frequency circuit device composed of hybrid ICs, comprises an insulated substrate, an active component fabricated on the insulated substrate and including a ground terminal for grounding high-frequency signal components, a first electrode fabricated on one surface of the insulated substrate and connected to the ground terminal, a ground conductor on the insulated substrate, an annular dielectric body placed on the ground conductor, a second electrode fabricated on an opposite surface of the insulated substrate in confronting relation to the ground conductor across the dielectric body and connected to the first electrode through a through hole defined in the insulated substrate, the ground terminal of the active component connected to ground high-frequency signal components through the first electrode, the through hole, the electrode, the dielectric body, and the ground conductor.

    Abstract translation: 由混合IC构成的高频电路装置包括：绝缘基板，在绝缘基板上制造的有源元件，具有用于接地高频信号元件的接地端子;在绝缘基板的一个表面上制造的第一电极， 到接地端子，绝缘基板上的接地导体，放置在接地导体上的环形电介质体，第二电极，其制造在绝缘基板的相对表面上，与介电体的接地导体面对面，并连接到 第一电极通过绝缘基板中限定的通孔，有源部件的接地端子通过第一电极，通孔，电极，电介质体和接地导体连接到地面高频信号部件。

    Capacitive chip carrier and multilayer ceramic capacitors
    118.
    发明授权
    Capacitive chip carrier and multilayer ceramic capacitors 失效
    电容芯片载体和多层陶瓷电容器

    公开(公告)号：US4349862A

    公开(公告)日：1982-09-14

    申请号：US176949

    申请日：1980-08-11

    Applicant: Christopher H. Bajorek ,  Dudley A. Chance ,  Chung W. Ho

    Inventor： Christopher H. Bajorek ,  Dudley A. Chance ,  Chung W. Ho

    IPC: H01L23/12 ,  H01G4/12 ,  H01G4/38 ,  H01L23/15 ,  H01L23/538 ,  H01L23/64 ,  H01L25/00 ,  H01L27/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/46

    CPC classification number: H01L23/642 ,  H01L23/15 ,  H01L23/5383 ,  H05K1/162 ,  H01L2224/16 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/09763 ,  H05K3/4611 ,  H05K3/4629

    Abstract: A chip carrier system for supporting electronic semiconductor chips is provided with a matched coefficient of thermal expansion as well as a high value of capacitance. The carrier provides both mechanical and electrical connections to the chip. A small sized interposer for a silicon chip possesses high capacitance. An array of dot capacitors is formed between laminated layers of ceramic material. In some cases, conductive surfaces are provided on the upper and lower surfaces of a thin film of ceramic material in which dielectric bodies are interspersed in an array of openings therein. The resultant ceramic dielectric combination has a coefficient of thermal expansion which matches the coefficient of thermal expansion of the silicon chip and the substrate thereby relieving stress upon the solder ball joints between the interposer and both the chip and the substrate. This minimizes the mechanical stress upon the solder ball joints during thermal cycling of the structure. Alternatively, an array of multilayer ceramic capacitors has an array of dielectric bodies located within holes in ceramic layers between capacitor plates, or entire arrays of capacitors are formed in the space between ceramic sheets.

    Abstract translation: 用于支持电子半导体芯片的芯片载体系统具有匹配的热膨胀系数以及高电容值。 载体提供与芯片的机械和电气连接。 用于硅芯片的小尺寸插入器具有高电容。 在陶瓷材料的层压层之间形成点阵电容器阵列。 在一些情况下，导电表面设置在陶瓷材料薄膜的上表面和下表面上，其中介电体散布在其中的开口阵列中。 所得到的陶瓷电介质组合具有与硅芯片和基板的热膨胀系数匹配的热膨胀系数，从而缓解了插入件与芯片和基板之间的焊球接头的应力。 这最小化了结构热循环过程中焊球接头处的机械应力。 或者，多层陶瓷电容器阵列具有位于电容器板之间的陶瓷层中的孔内的介电体阵列，或在陶瓷片之间的空间中形成整个电容器阵列。

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