公开(公告)号：US06858453B1

公开(公告)日：2005-02-22

申请号：US09416368

申请日：1999-10-12

Applicant: David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill

Inventor： David J. Corisis ,  Tracy Reynolds ,  Michael Slaughter ,  Daniel Cram ,  Leland R. Nevill

IPC: G01R1/04 ,  G01R31/28 ,  H01L23/495 ,  H01L23/544 ,  H05K3/30 ,  G01R31/26 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/66

CPC classification number: G01R31/2851 ,  G01R1/0408 ,  G01R31/2884 ,  H01L23/4951 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/303 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10696 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semicircle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract translation: 提供了具有与引线框一体的对准特征的集成电路。 集成电路包括与半导体管芯耦合的引线框架，并部分封装在绝缘材料中。 引线框架具有其中的对准特征。 对准特征包括在引线框架上切割出半圆形，突起，孔或槽的形式。 或者，对准特征包括可移除地耦合的突片。 集成电路测试完成后，对准标签从集成电路中取出。 对准特征也可以设置在附着于引线框架封装的一侧或内部的散热器上。

公开(公告)号：US20040171315A1

公开(公告)日：2004-09-02

申请号：US10746192

申请日：2003-12-26

Applicant: Delta Electronics Inc.

Inventor： Pei-Sheng Liao ,  Jui-Yuan Hsu ,  Bay Shao-Ru Su

IPC: H01R013/42

CPC classification number: H01R12/7023 ,  H01R12/7058 ,  H05K3/306 ,  H05K3/308 ,  H05K2201/0311 ,  H05K2201/10568 ,  H05K2201/1059 ,  H05K2201/10651 ,  H05K2201/1084 ,  H05K2201/10856 ,  H05K2203/167

Abstract: A joint structure of electronic element for linking circuit board and electronic element is provided. The joint structure of an electronic element for being electrically connected to a circuit board has at least one slot positioned thereon. And, the joint structure of the electronic element includes: at least one terminal which has a curved portion including a deflected angle with a normal line of a plane of the circuit board, wherein when the joint structure of the electronic element is connected with the slot, the terminal produces an elastic stress through suffering a jostle from the slot so as to urge against the slot for forming an electrical connection therebetween.

Abstract translation: 提供了用于连接电路板和电子元件的电子元件的接合结构。 用于电连接到电路板的电子元件的接合结构具有至少一个位于其上的槽。 并且，电子元件的接合结构包括：至少一个端子，其具有包括与电路板的平面的法线的偏转角度的弯曲部分，其中当电子元件的接合结构与槽 ，终端通过从槽中穿过约束而产生弹性应力，以便推动抵靠槽以在它们之间形成电连接。

公开(公告)号：US06784372B1

公开(公告)日：2004-08-31

申请号：US09579649

申请日：2000-05-26

Applicant: Albert T. Yuen ,  Pierre H. Mertz

Inventor： Albert T. Yuen ,  Pierre H. Mertz

IPC: H05K100

CPC classification number: H05K3/3442 ,  H05K3/366 ,  H05K2201/09036 ,  H05K2201/10454 ,  H05K2201/10537 ,  H05K2201/10568 ,  H05K2201/10984 ,  H05K2203/041 ,  Y02P70/613

Abstract: An orthogonal electrical connector using a ball edge array includes one or more stackable fiber optic transceivers, wherein each transceiver includes an electrical substrate, and arrays of solder, which is in form of solder balls or solder paste. The solder is held in predetermined position adjacent to the electrical traces on both sides of the electrical substrate inserted into voids on the molded housing and aligned to contact the electrical traces on the motherboard. The electrical traces on the electrical substrate and the motherboard are located close enough so that the solder physically touches both parts during the soldering process. The solder is reflowed by heat, and the melted solder “wicks up” the electrical traces on the electrical substrate by surface tension.

Abstract translation: 使用球边缘阵列的正交电连接器包括一个或多个可堆叠的光纤收发器，其中每个收发器包括电衬底和焊料阵列，其为焊球或焊膏的形式。 焊料保持在与插入模制外壳上的空隙中的电气基板的两侧上的电迹线相邻的预定位置，并对准以接触主板上的电迹线。 电气基板和母板上的电气迹线位置足够近，使焊料在焊接过程中物理接触两部分。 焊料通过热回流，并且熔化的焊料通过表面张力“汲取”电气基板上的电迹线。

公开(公告)号：US20040070067A1

公开(公告)日：2004-04-15

申请号：US10650433

申请日：2003-08-28

Inventor： Takayuki Tani ,  Takao Shibuya

IPC: H01L023/48

CPC classification number: H01L23/49816 ,  H01L23/3121 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/10166 ,  H05K2201/10568 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: It is difficult to check the mounted state of solder by means of visual inspection after the mounting of a semiconductor device according to a conventional art, in particular, a CSP-semiconductor device, to a substrate and a problem arises wherein defective products increase and yield decreases. Terminals 50, 51, 52 and 53 for external connection are exposed from second main surface 412 of first insulating substrate 41 in the semiconductor device according to the present invention. Thus, second insulating substrate 48 is adhered to second main surface 412 so as to surround the internal portions of these terminals for external connection. Thereby, second insulating substrate 48 serves as a background mirror so that the mounted state of deep portions of the solder can be ascertained at the time of visual inspection of the mounted state of solder after the mounting of the semiconductor device to the substrate. As a result, the mounted state of the solder can be inspected without failure so that reduction in the number of defective products and increased yield can be attained.

Abstract translation: 在将传统技术的半导体器件，特别是CSP半导体器件安装到衬底之后，通过目视检查难以检查焊料的安装状态，并且出现其中不良产品增加并产生的问题 减少 用于外部连接的端子50,51,52和53暴露于根据本发明的半导体器件中的第一绝缘基板41的第二主表面412。 因此，第二绝缘基板48粘附到第二主表面412，以便围绕这些端子的内部部分进行外部连接。 因此，第二绝缘基板48用作背景镜，使得在将半导体器件安装到基板之后，在目视检查焊料的安装状态时，可以确定焊料深部的安装状态。 结果，可以不发生故障地检查焊料的安装状态，从而可以实现不良产品的数量的减少和产量的提高。

公开(公告)号：US06710373B2

公开(公告)日：2004-03-23

申请号：US10201768

申请日：2002-07-22

Applicant: Shih-Yi Wang

Inventor： Shih-Yi Wang

IPC: H01L2302

CPC classification number: H01L33/62 ,  H01L2224/48091 ,  H01L2924/12041 ,  H01L2924/3025 ,  H05K3/303 ,  H05K2201/10106 ,  H05K2201/10568 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A photoelectric structure for surface mounting on a circuit board having a plurality of insertion holes includes at least a pair of fixation pins integrally extended downwards from a periphery of the mounting photoelectric element, and a pair of bended connections integrally extended downwards from a periphery of the mounting photoelectric element such that they are connected with the circuit board by welding, so as to facilitate the other pair of fixation pins to be inserted into the insertion holes of the circuit board for locating securely the photoelectric element for use in Surface Mount Device, SMD, and for enhancing effectively the position of the detection point as well as the degree of precision of the light emitting signal.

Abstract translation: 用于表面安装在具有多个插入孔的电路板上的光电结构包括从安装光电元件的周边向下一体地延伸的至少一对固定销，以及从所述安装光电元件的周边向下整体延伸的一对弯曲连接 安装光电元件，使其通过焊接与电路板连接，以便于另一对固定销插入电路板的插孔中，以安全地定位用于表面贴装器件的光电元件，SMD ，并且有效地提高检测点的位置以及发光信号的精度。

公开(公告)号：US20040017013A1

公开(公告)日：2004-01-29

申请号：US10621561

申请日：2003-07-18

Applicant: Oki Electric Industry Co., Ltd.

Inventor： Tadashi Yamaguchi

IPC: H01L023/48

CPC classification number: G01N33/573 ,  H01L23/3114 ,  H01L23/544 ,  H01L29/0657 ,  H01L2221/6834 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/10155 ,  H01L2924/10158 ,  H05K3/303 ,  H05K2201/09036 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2203/168 ,  Y02P70/613

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface having circuit elements formed thereon, a second main surface substantially opposite to the first main surface, and a plurality of side faces provided between the first main surface and the second main surface. The semiconductor device also includes a plurality of external terminals formed over the first main surface and respectively electrically connected to the circuit elements. The second main surface has a first steplike section which extends from a first side face of the plurality of side faces to a second side face opposite to the first side face.

Abstract translation: 半导体器件包括具有形成在其上的电路元件的第一主表面，与第一主表面基本相对的第二主表面和设置在第一主表面和第二主表面之间的多个侧面的半导体衬底。 半导体器件还包括形成在第一主表面上并分别电连接到电路元件的多个外部端子。 第二主表面具有从多个侧面的第一侧面延伸到与第一侧面相对的第二侧面的第一台阶状部。

公开(公告)号：US06682946B2

公开(公告)日：2004-01-27

申请号：US10119461

申请日：2002-04-10

Applicant: Jerrold L. King ,  Leland R. Nevill

Inventor： Jerrold L. King ,  Leland R. Nevill

IPC: H01L2166

CPC classification number: H05K3/303 ,  G01R31/2851 ,  G01R31/2884 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/0195 ,  Y02P70/613

Abstract: An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.

Abstract translation: 改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。 通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。 配合表面被布置成仅可实现一个可配合的位置。 基本上一致的表面等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。 一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

公开(公告)号：US06670720B2

公开(公告)日：2003-12-30

申请号：US09799179

申请日：2001-03-05

Applicant: Jerrold L. King ,  Leland R. Nevill

Inventor： Jerrold L. King ,  Leland R. Nevill

IPC: H01L2348

CPC classification number: H05K3/303 ,  G01R31/2851 ,  G01R31/2884 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/0195 ,  Y02P70/613

Abstract: An improved semiconductor chip package capable of independently aligning with testing equipment during the manufacturing phase of electrical testing. Independent alignment is realized by directly connecting the semiconductor chip package to the test alignment apparatus by fitting together two substantially conforming surfaces, one on the chip package and one on the alignment apparatus. The conforming surfaces are arranged so that only one matable position is achievable. The substantially conforming surfaces can equate to three substantially conical indentations on the chip package and three substantially conical protrusions or protuberances of substantially conforming size and depth extending from the alignment apparatus. Once fitted, the three protrusions suspend the semiconductor chip in a substantially horizontal plane so that electrical test contacts, also substantially in a horizontal plane, may be easily contacted with the conductive leads extending generally horizontally and co-planar from the semiconductor chip.

Abstract translation: 改进的半导体芯片封装，能够在电气测试制造阶段与测试设备独立对齐。 通过将两个基本上一致的表面（一个在芯片封装上）和一个在对准装置上装配在一起，将半导体芯片封装直接连接到测试对准装置，实现独立对准。 配合表面被布置成仅可实现一个可配合的位置。 基本上一致的表面可以等同于芯片封装上的三个基本上圆锥形的凹口，以及从对准装置延伸的基本上一致的尺寸和深度的三个基本上圆锥形的突起或突起。 一旦安装，三个突起将半导体芯片悬挂在基本上水平的平面中，使得电测试接触（也基本上在水平面）可以容易地与从半导体芯片大致水平并共面延伸的导电引线接触。

公开(公告)号：US20030111258A1

公开(公告)日：2003-06-19

申请号：US10020859

申请日：2001-12-13

Inventor： Tom E. Pearson ,  Christopher D. Combs ,  Arjang Fartash ,  Raiyomand Aspandiar

IPC: H01B017/00

CPC classification number: H05K3/305 ,  H01L2924/15151 ,  H05K3/3415 ,  H05K2201/09072 ,  H05K2201/10568 ,  H05K2201/10734 ,  H05K2203/1105 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: An apparatus to retain an assembled component on one side of a double-sided printed circuit board during reflow of other components subsequently positioned onto an opposite side of the double-sided printed circuit board and methods for manufacturing and using the same. Being formed from an epoxy material, the retainer is configured to be coupled with a component, which is then positioned onto a printed circuit board. During a subsequent solder reflow stage, an ambient temperature surrounding the printed circuit board increases, and the epoxy material is configured to enter a semi-liquid state, flowing onto, and adhering with, the printed circuit board. Upon reaching a typical solder reflow temperature, the liquefied epoxy material is configured to cure or harden, adhesively coupling the component with the printed circuit board. Thereby, the component is inhibited from separating from the printed circuit board when the printed circuit board is subsequently inverted, populated, and reflowed.

公开(公告)号：US20030107876A1

公开(公告)日：2003-06-12

申请号：US10310297

申请日：2002-12-05

Applicant: Alps Electric Co., Ltd.

Inventor： Norio Suzuki

IPC: H05K001/14

CPC classification number: H05K9/006 ,  H05K3/366 ,  H05K7/12 ,  H05K2201/048 ,  H05K2201/09645 ,  H05K2201/10568 ,  H05K2201/10598

Abstract: A structure for highly precisely and easily mounting an electronic circuit unit on a mother board without defective soldering, comprising a circuit board 3 provided with extending portions 3d having terminal patterns 8 formed thereon, a housing 2 for containing the circuit board 3 while permitting the extending portions 3d to protrude, and a mother board 5 having, formed therein, through holes 5a in which the extending portions 3d are to be inserted, having, formed thereon, wiring pattern (not shown) that is to be electrically connected to the terminal patterns 8, and permitting the extending portions 3d to be inserted in the through holes 5a so that the housing 2 is placed thereon. The circuit board 3 is provided with a protruded portion 3e which extends separately from the extending portions 3d and pushes the terminal patterns 8 onto the wiring pattern of the mother board 5. The mother board 5 is provided with an insertion hole 5b in which the protruded portion 3e is to be inserted being slightly deviated from the positions of the through holes 5a in which the extending portions 3d are to be inserted.

Abstract translation: 一种将电子电路单元高精度地且容易地安装在母板上而没有焊接不良的结构，包括：电路板3，其设置有形成有端子图案8的延伸部分3d;容纳电路板3的壳体2，同时允许延伸 在其上形成有通孔5a，其中形成有延伸部3d插入其中的母板5，母板5形成在其上形成有电连接到端子图案的布线图案（未示出） 如图8所示，并且允许延伸部分3d插入到通孔5a中，使得壳体2放置在其上。 电路板3设置有与延伸部3d分开延伸的突出部3e，将端子图案8推压到母板5的布线图案上。母板5设置有插入孔5b，突出部 部分3e将被插入，以从其中插入延伸部分3d的通孔5a的位置稍微偏离。