公开(公告)号：US20230074430A1

公开(公告)日：2023-03-09

申请号：US17447029

申请日：2021-09-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  Gwang Kim ,  Junho Ye

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/60 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.

公开(公告)号：US20230067475A1

公开(公告)日：2023-03-02

申请号：US17445908

申请日：2021-08-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： NamJu Cho ,  YoungCheol Kim ,  HaengCheol Choi

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01Q1/22

Abstract: A semiconductor device has a substrate and a first electrical component disposed over a first surface of the substrate. An RF antenna interposer is disposed over the substrate with the first electrical component connected to a first antenna disposed on a surface of the antenna interposer. An area of the antenna interposer is substantially the same as an area of the substrate. The first antenna disposed on the surface of the antenna interposer has a plurality of islands of conductive material. Alternatively, the first antenna disposed on the surface of the antenna interposer has a spiral shape of conductive material. A second antenna can be disposed on the surface of the antenna interposer connected to a second electrical component disposed over the substrate. A second electrical component can be disposed over a second surface of the substrate opposite the first surface of the substrate.

公开(公告)号：US20230012958A1

公开(公告)日：2023-01-19

申请号：US17936714

申请日：2022-09-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim ,  Byung Joon Han

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/786 ,  H01L21/784 ,  H01L21/782 ,  H01L21/82 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

公开(公告)号：US11444035B2

公开(公告)日：2022-09-13

申请号：US16991370

申请日：2020-08-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoWang Koo ,  SungWon Cho ,  BongWoo Choi ,  JiWon Lee

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/28 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/60

Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.

公开(公告)号：US11434561B2

公开(公告)日：2022-09-06

申请号：US17032437

申请日：2020-09-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： OhHan Kim ,  HunTeak Lee ,  Sell Jung ,  HeeSoo Lee

IPC: C23C14/50 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  C23C14/34

Abstract: A semiconductor manufacturing device has a cooling pad with a plurality of movable pins. The cooling pad includes a fluid pathway and a plurality of springs disposed in the fluid pathway. Each of the plurality of springs is disposed under a respective movable pin. A substrate includes an electrical component disposed over a surface of the substrate. The substrate is disposed over the cooling pad with the electrical component oriented toward the cooling pad. A force is applied to the substrate to compress the springs. At least one of the movable pins contacts the substrate. A cooling fluid is disposed through the fluid pathway.

公开(公告)号：US11355452B2

公开(公告)日：2022-06-07

申请号：US17068482

申请日：2020-10-12

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Dong Won Son ,  Byeonghoon Kim ,  Sung Ho Choi ,  Sung Jae Lim ,  Jong Ho Shin ,  SungWon Cho ,  ChangOh Kim ,  KyoungHee Park

IPC: H01L23/34 ,  H01L23/28 ,  H01L21/00 ,  H05K7/20 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US20220157739A1

公开(公告)日：2022-05-19

申请号：US16950295

申请日：2020-11-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： HunTeak Lee ,  KyungHwan Kim ,  HeeSoo Lee ,  ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L21/56

Abstract: A semiconductor package has a substrate, a first component disposed over the substrate, an encapsulant deposited over the first component, and a second component disposed over the substrate outside the encapsulant. A metal mask is disposed over the second component. A shielding layer is formed over the semiconductor package. The metal mask after forming the shielding layer. The shielding layer is optionally formed on a contact pad of the substrate while a conic area above the contact pad that extends 40 degrees from vertical remains free of the encapsulant and metal mask while forming the shielding layer. Surfaces of the metal mask and encapsulant oriented toward the contact pad can be sloped. The metal mask can be disposed and removed using a pick-and-place machine.

公开(公告)号：US11145603B2

公开(公告)日：2021-10-12

申请号：US16005387

申请日：2018-06-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  KyoungHee Park ,  Yaojian Lin ,  KyoWang Koo ,  In Sang Yoon ,  SeungYong Chai ,  SungWon Cho ,  SungSoo Kim ,  Hun Teak Lee ,  DeokKyung Yang

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L25/16 ,  H01L21/56

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

公开(公告)号：US20210301390A1

公开(公告)日：2021-09-30

申请号：US17032437

申请日：2020-09-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： OhHan Kim ,  HunTeak Lee ,  SeIl Jung ,  HeeSoo Lee

IPC: C23C14/50 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  C23C14/34

Abstract: A semiconductor manufacturing device has a cooling pad with a plurality of movable pins. The cooling pad includes a fluid pathway and a plurality of springs disposed in the fluid pathway. Each of the plurality of springs is disposed under a respective movable pin. A substrate includes an electrical component disposed over a surface of the substrate. The substrate is disposed over the cooling pad with the electrical component oriented toward the cooling pad. A force is applied to the substrate to compress the springs. At least one of the movable pins contacts the substrate. A cooling fluid is disposed through the fluid pathway.

公开(公告)号：US11024561B2

公开(公告)日：2021-06-01

申请号：US16885640

申请日：2020-05-28

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.