公开(公告)号：US20210089221A1

公开(公告)日：2021-03-25

申请号：US17031640

申请日：2020-09-24

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau

IPC: G06F3/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

公开(公告)号：US20210083005A1

公开(公告)日：2021-03-18

申请号：US16948575

申请日：2020-09-23

Applicant: Unity Semiconductor Corporation

Inventor： Bruce Lynn Bateman

IPC: H01L27/24 ,  H01L45/00

Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20200302973A1

公开(公告)日：2020-09-24

申请号：US16844487

申请日：2020-04-09

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: G11C5/02 ,  G11C13/00 ,  G11C8/00 ,  G11C11/00 ,  H01L21/82 ,  H01L45/00

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

公开(公告)号：US20200271718A1

公开(公告)日：2020-08-27

申请号：US16087056

申请日：2017-03-14

Applicant: UNITY SEMICONDUCTOR

Inventor： Philippe GASTALDO ,  Mayeul DURAND DE GEVIGNEY ,  Tristan COMBIER

IPC: G01R31/308 ,  G01R31/28

Abstract: A method for inspecting a wafer including: rotating the wafer about an axis of symmetry (X) perpendicular to a main wafer surface (S); emitting, from a light source coupled with an interferometric device, two incident light beams, to form, at the intersection between the two beams, a measurement volume (V) containing interference fringes so that a region of the main surface (S) of the wafer passes through a fringe, the dimension (Dy) of the measurement volume in a radial direction of the wafer being between 5 and 100 μm; collecting a portion of the light scattered by the wafer region; acquiring the collected light and emitting a signal representing the variation in the collected light intensity as a function of time; and detecting, a frequency component in the collected light, the frequency being the time signature of a defect passage through the measurement volume.

公开(公告)号：US20190392895A1

公开(公告)日：2019-12-26

申请号：US16460708

申请日：2019-07-02

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  H03K3/356 ,  H03K19/0185 ,  G11C8/10 ,  G11C8/08

Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

公开(公告)号：US10453525B2

公开(公告)日：2019-10-22

申请号：US15823270

申请日：2017-11-27

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Robert Norman

IPC: G11C13/00 ,  G11C5/02 ,  G11C11/16 ,  G11C5/00

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

公开(公告)号：US20190279712A1

公开(公告)日：2019-09-12

申请号：US16297303

申请日：2019-03-08

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00 ,  G11C5/06 ,  G11C7/04 ,  G11C7/00 ,  G11C16/24 ,  G11C7/12 ,  G11C5/08 ,  G11C7/18

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US20190137265A1

公开(公告)日：2019-05-09

申请号：US16092751

申请日：2017-04-05

Applicant: UNITY SEMICONDUCTOR

Inventor： Jean-François BOULANGER ,  Benoît THOUY

IPC: G01B11/24 ,  G01B9/02 ,  G01B11/06 ,  H01L21/66

Abstract: A method for the inspection and measurement of a face of an object having at least two surfaces staggered depthwise with respect to one another, the surfaces forming in particular a step or a trench on/in the face, the method including the following steps: measuring an interferometric signal, called measured signal, at several points, called measurement points, of the inspected face; for at least one measurement point, extracting the measured signal relative to at least one, in particular to each, surface, the extraction providing for the measurement point an interferometric signal, called individual signal, for the surface; profilometric analysis of the individual signals, independently for each surface. Also included is a system for the inspection and measurement of a face of an object implementing such a method.

公开(公告)号：US20190103161A1

公开(公告)日：2019-04-04

申请号：US16126101

申请日：2018-09-10

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  G11C11/21

CPC classification number: G11C13/0033 ,  G11C11/21 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

公开(公告)号：US20190013070A1

公开(公告)日：2019-01-10

申请号：US16004705

申请日：2018-06-11

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Chang Hua Siau

IPC: G11C13/00 ,  H03K19/0185 ,  H03K3/356 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.