公开(公告)号：US09018664B2

公开(公告)日：2015-04-28

申请号：US14144111

申请日：2013-12-30

Applicant: Nichia Corporation

Inventor： Masafumi Kuramoto ,  Satoru Ogawa ,  Miki Niwa

IPC: H01L33/62 ,  H01L33/44 ,  H01L23/00 ,  H01L23/08 ,  H01L23/29 ,  H01L23/495 ,  H01S5/022

CPC classification number: H01L33/44 ,  H01L23/08 ,  H01L23/293 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2712 ,  H01L2224/2745 ,  H01L2224/275 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83487 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0541 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/201 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/3025 ,  H01L2933/0066 ,  H01S5/0226 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2224/05599

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, temporarily bonding the semiconductor element and the base by applying a pressure or an ultrasonic vibration to the semiconductor element or the base, and permanently bonding the semiconductor element and the base by applying heat having a temperature of 150 to 900° C. to the semiconductor device and the base.

Abstract translation: 本发明的目的是提供一种用于制造具有低电阻的导电构件的方法，并且使用不含粘合剂的低成本稳定的导电材料组合物获得导电构件。 一种制造半导体器件的方法，其中设置在基底表面上的银或氧化银和设置在半导体元件的表面上的银或银氧化物结合，包括以下步骤：将半导体元件布置在基底上，使得银 或设置在半导体元件的表面上的氧化银与设置在基板的表面上的银或氧化银接触，通过向半导体元件或基底施加压力或超声波振动来临时接合半导体元件和基座 并且通过向半导体器件和基底施加温度为150至900℃的热而将半导体元件和基底永久地接合。

公开(公告)号：US20150102507A1

公开(公告)日：2015-04-16

申请号：US14511158

申请日：2014-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol-woo LEE ,  Ji-han KO

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/06135 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29082 ,  H01L2224/29084 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32053 ,  H01L2224/32056 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45184 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/92147 ,  H01L2224/92165 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/06 ,  H01L2924/10161 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/066 ,  H01L2924/05442 ,  H01L2224/83

Abstract: Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

Abstract translation: 提供了可以防止堆叠的半导体芯片的变形并使半导体封装尺寸最小化的半导体封装。 半导体封装包括封装基底基板，堆叠在封装基底基板上的下部芯片，堆叠在下部芯片上的上部芯片，以及附接到上部芯片的底表面上的至少覆盖的第一芯片附着膜（DAF） 下部芯片的一部分。 第一DAF可以是多层膜，其包括接触上芯片的底表面的第一附着层和附接到第一附着层的底部的第二附着层，以覆盖下层的侧表面的至少一部分 芯片。

公开(公告)号：US20140353818A1

公开(公告)日：2014-12-04

申请号：US13909133

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Ottmar GEITNER ,  Wolfram HABLE ,  Andreas Grassmann ,  Frank Winter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/89 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/26135 ,  H01L2224/29005 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/30181 ,  H01L2224/83048 ,  H01L2224/83139 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/97 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer

Abstract translation: 提供一种制造包括两个基板的功率模块的方法，其中所述方法包括在第一基板之上设置第一厚度的补偿层; 在补偿层之上设置第二衬底; 以及在所述第二衬底设置在所述补偿层上之后，将所述补偿层的厚度从所述第一厚度减小到第二厚度

公开(公告)号：US08823155B2

公开(公告)日：2014-09-02

申请号：US13275430

申请日：2011-10-18

Applicant: Toshio Nakasaki

Inventor： Toshio Nakasaki

IPC: H01L27/00 ,  H01L21/76 ,  H01L21/683 ,  H01L21/764 ,  H01L21/786 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768 ,  H01L25/18 ,  H01L21/304 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L21/3043 ,  H01L21/6836 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/786 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/02313 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/056 ,  H01L2224/06131 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/01019 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.

Abstract translation: 半导体器件包括：第一半导体芯片，包括第一表面，第二表面和布置在第一表面上的第一端子;第二半导体芯片，包括第一表面，第二表面和第二端子，所述第二表面布置在第二表面的第二表面上 半导体芯片，包括结合到第一半导体芯片和第二半导体芯片的第二表面的第一表面的支撑基板，以及形成在支撑基板的第一表面上的隔离槽。 隔离包括分别从第一半导体芯片和第二半导体芯片的相对侧表面连续延伸的一对侧表面，并且隔离槽形成为支撑基板，以从支撑基板的第一表面延伸。 隔离槽的深度小于支撑基板的厚度。

公开(公告)号：US08735219B2

公开(公告)日：2014-05-27

申请号：US13599023

申请日：2012-08-30

Applicant: Paul M. Enquist ,  Gaius Gillman Fountain

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain

IPC: H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Abstract translation: 一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。 第一绝缘材料直接接合到第二绝缘材料上。 去除第一衬底的一部分以留下剩余部分。 具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。 粘合的基底被加热以促进第一和第二接触结构之间的电接触。 在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

公开(公告)号：US08439249B2

公开(公告)日：2013-05-14

申请号：US12567434

申请日：2009-09-25

Applicant: Roland Speckels ,  Thomas Licht ,  Karsten Guth

Inventor： Roland Speckels ,  Thomas Licht ,  Karsten Guth

IPC: B23K20/08 ,  H01L21/00

CPC classification number: H01L21/67092 ,  H01L21/6835 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/93 ,  H01L25/072 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/78743 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/01028

Abstract: A device and a method for making a semiconductor device including bonding a first bonding partner to a second bonding partner. The device comprises a lower tool and an upper tool, the upper tool including a plunger having a bottom side facing the lower tool at which bottom side a vacuum is creatable, so that the first bonding partner can be picked up by vacuum from the upper tool and positioned on the second bonding partner.

Abstract translation: 一种用于制造半导体器件的器件和方法，包括将第一结合伙伴接合到第二接合伙伴。 所述装置包括下部工具和上部工具，所述上部工具包括柱塞，所述柱塞具有面向所述下部工具的底侧，在所述下部工具的下侧可创建真空，从而可以从所述上部工具通过真空拾取所述第一焊接对象 并且位于第二粘合伙伴上。

公开(公告)号：US20120104602A1

公开(公告)日：2012-05-03

申请号：US13379273

申请日：2010-06-23

Applicant: Kenji Nanba

Inventor： Kenji Nanba

IPC: H01L23/485 ,  H01L21/28

CPC classification number: H01L24/11 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/10126 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/27416 ,  H01L2224/27515 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29018 ,  H01L2224/29022 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/3512 ,  H01L2924/00

Abstract: [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided.[Means for solving the problem] The semiconductor device has: an electrode; an insulating part having an opening on the electrode; a protruding part formed on the electrode; a protecting part which is formed at the periphery of the protruding part and electrically isolates the protruding part; and a bonding part which is formed on the protecting part by being spaced apart from the protruding part. An upper surface of the protruding part, an upper surface of the protecting part, and an upper surface of the bonding part form the same plane.

Abstract translation: [问题]提供了一种实现细间距，高吞吐量和高连接可靠性的半导体器件，特别是在倒装芯片安装中。 还提供了一种用于制造半导体器件的方法和使用该半导体器件的电路器件。 [解决问题的手段]半导体器件具有：电极; 在所述电极上具有开口的绝缘部; 形成在所述电极上的突出部; 保护部，其形成在突出部的周围，并且使突出部电隔离; 以及通过与所述突出部分间隔开地形成在所述保护部上的接合部。 突出部的上表面，保护部的上表面和接合部的上表面形成同一平面。

公开(公告)号：US20120038060A1

公开(公告)日：2012-02-16

申请号：US12855765

申请日：2010-08-13

Applicant: Jui-Hung CHENG

Inventor： Jui-Hung CHENG

IPC: H01L23/12 ,  H01L21/50

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27416 ,  H01L2224/2783 ,  H01L2224/27831 ,  H01L2224/29015 ,  H01L2224/29019 ,  H01L2224/2919 ,  H01L2224/32055 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation.

Abstract translation: 提供堆叠载体和堆垛方法。 在具有相同形状的晶片和堆叠载体之间使用层叠方法。 堆叠方法包括以下步骤。 首先，在载体的表面上涂布粘合剂层。 然后，对应于载体边缘的粘合剂层被部分地去除，从而限定至少一个粘合剂层压痕。 之后，通过具有粘合剂层压痕的粘合剂层将晶片堆叠在载体上。

公开(公告)号：US20110049707A1

公开(公告)日：2011-03-03

申请号：US12850828

申请日：2010-08-05

Applicant: Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

Inventor： Masaharu Seto ,  Soichi Yamashita ,  Hirokazu Ezawa

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02311 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/29011 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29076 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/0132 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.

Abstract translation: 根据一个实施例，半导体器件包括电极焊盘，保护层，凸块和树脂层。 电极焊盘形成在半导体衬底上。 保护层包括形成在电极焊盘的位置的焊盘开口。 凸块形成在焊盘开口中并电连接到电极焊盘。 树脂层具有设置在树脂层和凸块之间的空间，并通过金属层形成在保护层上。 树脂层通过使用粘合树脂材料形成。

公开(公告)号：US20100289144A1

公开(公告)日：2010-11-18

申请号：US12465839

申请日：2009-05-14

Applicant: Mukta G. Farooq ,  Subramanian S. lyer

Inventor： Mukta G. Farooq ,  Subramanian S. lyer

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L24/94 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/16 ,  H01L24/28 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer.

Abstract translation: 制作3D集成电路和3D集成电路结构的方法。 连接到第二半导体结构的第一半导体结构。 每个半导体结构包括半导体晶片，半导体晶片上的线的前端（FEOL）布线，FEOL布线上的线的后端（BEOL）布线，BEOL布线上的绝缘体层和金属层 绝缘体层。 第一半导体结构与第二半导体结构对准，使得每个半导体结构的金属层彼此面对。 每个半导体结构的金属层通过金属 - 金属键彼此接触并彼此结合，其中结合的金属层形成电隔离层。