公开(公告)号：US20020171065A1

公开(公告)日：2002-11-21

申请号：US10113733

申请日：2002-04-01

Applicant: Nashua Corporation

Inventor： Darren Lochun ,  John J. Ireland

IPC: H01B001/00 ,  H01C001/00

CPC classification number: H05K3/246 ,  G08B13/244 ,  H01F5/003 ,  H01F41/041 ,  H01F2017/006 ,  H05K1/036 ,  H05K1/095 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/245 ,  H05K3/38 ,  H05K2201/0129 ,  H05K2201/0347 ,  H05K2203/0278 ,  H05K2203/107 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/2982 ,  Y10T428/31645 ,  Y10T428/31721 ,  Y10T428/31786 ,  Y10T428/31855 ,  Y10T428/31909 ,  Y10T428/31928 ,  Y10T428/31931 ,  Y10T428/31935

Abstract: Disclosed is a circuit element that includes a thermoplastic substrate and a conductive trace at least partially embedded in the thermoplastic substrate. Also disclosed is a method of forming a circuit element. The method includes the steps of providing a thermoplastic substrate having a softening temperature, printing a conductive ink onto the thermoplastic substrate to form a trace, and embedding the trace into the thermoplastic substrate by heating the thermoplastic substrate to a temperature above about the softening temperature about the trace.

Abstract translation: 公开了一种电路元件，其包括热塑性基材和至少部分地嵌入热塑性基材中的导电迹线。 还公开了形成电路元件的方法。 该方法包括以下步骤：提供具有软化温度的热塑性基材，将导电油墨印刷到热塑性基材上以形成痕迹，并通过将热塑性基材加热到高于约软化温度约 痕迹。

公开(公告)号：US06476775B1

公开(公告)日：2002-11-05

申请号：US09524505

申请日：2000-03-13

Applicant: Robert R. Oberle

Inventor： Robert R. Oberle

IPC: H01Q136

CPC classification number: H01Q1/2225 ,  G06K19/07749 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q9/27 ,  H05K1/095 ,  H05K1/165 ,  H05K3/242 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2203/0191 ,  H05K2203/0769 ,  Y10T29/49016

Abstract: A metalized circuit suitable for application as a radio frequency antenna is produced by forming an antenna coil pattern on a flexible substrate. The antenna coil pattern is formed using a conductive ink which is patterned on the substrate. The conductive ink is cured and an electrical-short layer is formed across the coils of the conductive ink pattern. An insulating layer is formed over top of the electrical-short layer, a metal layer electroplated on top of the conductive layer, and then the electrical-short layer is removed. The use of the electrical-short layer during the electroplating allows for the voltage at the different points on the conductive ink layer to be relatively similar, so that a uniform electroplate layer is formed on top of the conductive ink layer. This results in a better quality radio frequency antenna at a reduced cost.

Abstract translation: 通过在柔性基板上形成天线线圈图案来制造适用于射频天线的金属化电路。 天线线圈图案使用在衬底上图案化的导电油墨形成。 导电油墨固化，并且在导电油墨图案的线圈之间形成电短路层。 绝缘层形成在电 - 短层的顶部，电镀在导电层的顶部上的金属层，然后去除电 - 短层。 在电镀期间使用电 - 短层允许导电油墨层上的不同点处的电压相对相似，使得在导电油墨层的顶部上形成均匀的电镀层。 这导致了降低成本的更好质量的射频天线。

公开(公告)号：US06459585B1

公开(公告)日：2002-10-01

申请号：US09520840

申请日：2000-03-08

Applicant: Leif Bergstedt ,  Per Ligander

Inventor： Leif Bergstedt ,  Per Ligander

IPC: H05K720

CPC classification number: H05K1/0204 ,  H05K3/4046 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/10416 ,  H05K2201/1059 ,  H05K2201/10689

Abstract: A component (16) mounted on the board (20) is cooled by a cooling surface (15) in contact with a heat sink element in the form of a metal stud (8) which, in turn, may be connected to an outer cooling surface. One method of achieving this is to form holes (4) in a laminate (1), etching patterns (5), placing a metal stud (8) in the hole (4), applying a dielectric (9) to the upper and lower side of the laminate (1), forming openings (14) in the dielectric (9), and thereafter metal plating the entire circuit board and etching further patterns. Component 16 can then be mounted on the printed circuit board (20). A heat sink element (8) includes a cutting edge (18) and can be used beneficially in conjunction with one embodiment of the method.

Abstract translation: 安装在板（20）上的部件（16）被冷却表面（15）冷却，该冷却表面与金属螺柱（8）形式的散热元件接触，冷却表面又可以连接到外部冷却 表面。 实现这一点的一种方法是在层叠体（1）中形成孔（4），蚀刻图案（5），将金属柱（8）放置在孔（4）中，将电介质（9）施加到上下 （1）的侧面，在电介质（9）中形成开口（14），然后金属电镀整个电路板并蚀刻其它图案。 组件16然后可以安装在印刷电路板（20）上。 散热元件（8）包括切割边缘（18）并且可以有益地使用该方法的一个实施例。

公开(公告)号：US20020132502A1

公开(公告)日：2002-09-19

申请号：US10053052

申请日：2002-01-18

Inventor： Ian James Stafford Gray ,  John Impay

IPC: H05K001/00

CPC classification number: H05K3/20 ,  H01R24/50 ,  H01R43/18 ,  H01R43/24 ,  H01R2103/00 ,  H05K1/0284 ,  H05K1/119 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2201/09809 ,  H05K2203/1476 ,  H05K2203/175 ,  Y10S439/931

Abstract: An electrical component includes an initial structure (40) molded of an insulative first material and having a plurality of regions (81, 82, 83) that each forms a passage (42), with the regions being largely separated to leave gaps (90, 92, 94) between them, but with the regions joined by small tabs (44). The initial structure is plated everywhere, including along the passages and on the tabs. A quantity of second insulative material (108) is overmolded to the plated initial structure to fill the gaps between them but not some portions of the passages. The tabs then can be cut away to electrically isolate the platings on the different regions, and to thereby electrically isolated contacts, such as the outer conductors of coaxial connectors, installed in the passages while the regions that form the passages are mechanically held together by the overmolding second material.

公开(公告)号：US20020131229A1

公开(公告)日：2002-09-19

申请号：US09812261

申请日：2001-03-19

Applicant: International Business Machines Corporation

Inventor： Gerald W. Jones ,  John M. Lauffer ,  Voya R. Markovich ,  Thomas R. Miller ,  James P. Paolletti ,  Konstantinos I. Papathomas ,  James R. Stack

IPC: F23Q003/01

CPC classification number: H05K3/462 ,  H05K1/115 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0554

Abstract: A structure of and method for producing a multilayer printed or wiring circuit board, and more particularly a method producing so-called z-axis or multilayer electrical interconnections in a hierarchial wiring structure in order to be able to provide for an increase in the number of inputs and outputs (I/O) in comparison with a standard printed wiring board (PWB) arrangement, and a printed wiring board produced by the method.

Abstract translation: 更具体地说，在分层布线结构中制造所谓的z轴或多层电互连的方法的结构和方法，以便能够提供数量的增加 与标准印刷线路板（PWB）布置相比，输入和输出（I / O）和通过该方法制造的印刷线路板。

公开(公告)号：US06359337B1

公开(公告)日：2002-03-19

申请号：US09407151

申请日：1999-09-28

Applicant: Ronald Keukelaar ,  Leonard Nanis

Inventor： Ronald Keukelaar ,  Leonard Nanis

IPC: H01L2348

CPC classification number: G01R1/06761 ,  G01R3/00 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/241 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

Abstract: An improved wear resistant bump contact is produced by the inclusion of small particles of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. Nitride, borides, silicides, carbides are typical interstitial compounds suitable for use in satisfying these desirable attributes. In one preferred example, a nickel bulk material and silicon carbide particles are utilized. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer of noble, non-oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad. Rhodium and ruthenium are suitable metals and can be electrodeposition over the composite bump structure.

Abstract translation: 通过在接触凸块的导电材料中包含硬质材料的小颗粒，优选通过在凸块块状材料的电镀时共沉积来制造改进的耐磨凸点接触。 硬质材料的小颗粒的理想特性包括小的颗粒尺寸，硬度大于接触凸块的散装材料的硬度，与电镀条件的兼容性和导电性。 氮化物，硼化物，硅化物，碳化物是适合用于满足这些所需属性的典型间隙化合物。 在一个优选实施例中，使用镍本体材料和碳化硅颗粒。 在一个实施例中，金属 - 颗粒共沉积材料的凸起由贵金属非氧化金属的薄盖层涂覆，以防止由于接触而从焊盘断开而导致电弧侵蚀。 铑和钌是合适的金属，可以电沉积在复合凸块结构上。

公开(公告)号：US06350365B1

公开(公告)日：2002-02-26

申请号：US09634783

申请日：2000-08-09

Applicant: Toshinori Koyama ,  Noritaka Katagiri

Inventor： Toshinori Koyama ,  Noritaka Katagiri

IPC: C25D502

CPC classification number: H01L21/486 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K3/28 ,  H05K3/426 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2224/0401

Abstract: A method of producing a multilayer circuit board comprising a core substrate and a plurality of layers of wiring lines on both sides of the core substrate with an insulation layer being interposed therebetween; the layers of wiring lines on both sides being interconnected by conducting members provided on the inside walls of through holes going through the core substrate, and the interposed insulation layer. The method further comprising, wiring lines with an upper layer of wiring lines wherein the conducting member on the inside wall of the through hole and the via are formed in separate steps. The method can provide a multilayer circuit board which can advantageously be used to mount a chip or device thereon having an increased number of electrodes or terminals.

Abstract translation: 一种制造多层电路板的方法，所述多层电路板包括芯基板和在芯基板的两侧上的多层布线，绝缘层被插入其间; 两侧的布线层由设置在穿过芯基板的通孔的内壁上的导电构件和插入的绝缘层互连。 所述方法还包括：布线与布线的上层，其中通孔的内壁上的导电构件和通孔分开形成。 该方法可以提供可以有利地用于安装其上具有增加数量的电极或端子的芯片或器件的多层电路板。

公开(公告)号：US06303881B1

公开(公告)日：2001-10-16

申请号：US09649169

申请日：2000-08-25

Applicant: John LeRoy Parker, Jr. ,  Pamela L. Miscikowski

Inventor： John LeRoy Parker, Jr. ,  Pamela L. Miscikowski

IPC: H01R1204

CPC classification number: H05K3/4069 ,  H01R12/523 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/426 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0959 ,  H05K2203/1461

Abstract: An insulator substrate or printed circuit board (PCB) having a filled and plated via is provided. The plated via is filled with an electrically conductive fill composition. A conductive cap layer is formed on both ends of the conductive fill composition in the via and the major surfaces of the insulator substrate and can be bonded to a surface mount contact as a land or a pad.

Abstract translation: 提供具有填充和电镀通孔的绝缘体基板或印刷电路板（PCB）。 电镀通孔填充有导电填料组合物。 导电盖层形成在导电填料组合物的通孔和绝缘体基底的主表面的两端上，并且可以作为焊盘或焊盘接合到表面安装触头。

公开(公告)号：US06225035B1

公开(公告)日：2001-05-01

申请号：US09040635

申请日：1998-03-18

Applicant: Min-xian Zhang ,  Vernon L. Brown ,  George E. White ,  Lola Conway

Inventor： Min-xian Zhang ,  Vernon L. Brown ,  George E. White ,  Lola Conway

IPC: G03F740

CPC classification number: H01C17/0652 ,  H01C17/06586 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/184 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2203/0514 ,  H05K2203/1453 ,  H05K2203/1461

Abstract: A process for forming a resistor whose dimensions can be accurately determined by a photoimaging process, thereby yielding a resistor whose size and resistance value render the resistor a viable alternative to discrete chip resistors. The resistor is formed of a photoimageable resistive thick-film material that enables the dimensions of a resistor to be determined directly by photodefinition instead of conventional screen printing. Electrically-conductive terminations are provided that determine the electrical length of the resistor. The terminations may be formed prior to depositing the resistive layer, or after the resistive layer has been photoimaged and developed. If the latter approach is used, the terminations may be formed by depositing a photoimageable layer on the resistor, photoimaging and developing the photoimageable layer so as to form openings that expose regions of the resistor, and then plating, e.g., electrolessly plating, a conductive material on the exposed regions of the resistor to form terminations that overlie the resistor. Alternatively, by formulating the photoimageable layer to be plateable, a second photoimageable layer can be deposited on the plateable photoimageable layer prior to plating the conductive material, and then photoimaged and developed to form openings that expose regions of the plateable photoimageable layer that are adjacent the regions of the resistor exposed by the openings in the plateable photoimageable layer. Thereafter, the conductive material can be plated on the regions of the resistor and the plateable photoimageable layer exposed by the openings to yield terminations and connectors to the resistor.

Abstract translation: 一种形成电阻器的工艺，其尺寸可以通过光成像工艺精确地确定，从而产生电阻器，其尺寸和电阻值使得电阻器成为分立片式电阻器的可行替代品。 电阻器由可光成像的电阻厚膜材料形成，其能够通过光定义直接确定电阻器的尺寸，而不是传统的丝网印刷。 提供了确定电阻器电气长度的导电端子。 终端可以在沉积电阻层之前或者在电阻层被光刻和显影之后形成。 如果使用后一种方法，可以通过在电阻器上沉积可光成像层来形成端接，光成像和显影可光成像层，以便形成暴露电阻器区域的开口，然后电镀，例如无电镀，导电 电阻器的暴露区域上的材料，以形成覆盖在电阻器上的端子。 或者，通过配制可成像的可光成像层，在镀覆导电材料之前，可将第二可光成像层沉积在可平印光致成像层上，然后进行光刻和显影以形成露出可平版光成像层的区域的开口， 由电镀光可成像层中的开口露出的电阻器区域。 此后，可以将导电材料电镀在由开口露出的电阻器和可平板化光成像层的区域上，以产生端子和连接器到电阻器。

公开(公告)号：US06222272B1

公开(公告)日：2001-04-24

申请号：US09173683

申请日：1998-10-16

Applicant: Yoshinari Takayama ,  Kazuo Ouchi ,  Atsushi Hino

Inventor： Yoshinari Takayama ,  Kazuo Ouchi ,  Atsushi Hino

IPC: H01L2941

CPC classification number: H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/095 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In a film carrier with a conductive circuit formed, an opening is formed in a particular position relative to where the conductive path is to be formed. The opening is a through-hole, filled with a conductive material to form a conductive path. The conductive circuit has a concave face, provided according to certain formulae. The film carrier can cope with a fine-pitched and highly dense mounting, while prohibiting pulling out of the conductive path by an external force. The film carrier does not suffer from fallout of the conductive path, and has increased electrical connection reliability.

Abstract translation: 在形成有导电电路的薄膜载体中，相对于要形成导电路径的特定位置形成开口。 开口是通孔，填充有导电材料以形成导电路径。 导电电路具有根据某些公式提供的凹面。 薄膜载体可以处理细调和高度密集的安装，同时禁止通过外力从导电路径拉出。 电影载体不会受到导电路径的影响，并且具有增加的电连接可靠性。