公开(公告)号：US06360431B1

公开(公告)日：2002-03-26

申请号：US09853279

申请日：2001-05-11

Applicant: Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

Inventor： Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

IPC: H05K330

CPC classification number: H05K1/141 ,  G06F1/189 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09345 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

公开(公告)号：US06204712B1

公开(公告)日：2001-03-20

申请号：US09439077

申请日：1999-11-12

Applicant: Sergio D. Camerlo

Inventor： Sergio D. Camerlo

IPC: G06F104

CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0215 ,  H05K1/0231 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract translation: 描述了简单地实际上没有成本，并且仅使用标准时钟驱动器和简单，便宜的电气部件来大大降低时钟数字电路中的时序不确定性的方法和装置。 该方法包括通过控制时钟偏移和时钟抖动来最小化时序不确定性的步骤。 通过将多行时钟的输出结合在布置在印刷电路板（PCB）上的电容金属岛上来消除本征时钟偏移。 通过使用匹配长度的宽的相对较高电容的迹线来控制外部时钟偏移，并且布置在PCB的单个公共信号层上，每个通向相应的接收器电路并且相同地终止。 通过电气隔离PCB的区域来控制时钟抖动，将时钟驱动器设置在该区域中以使噪声最小化，并向该区域提供安静的局部电源和接地。

公开(公告)号：US5544018A

公开(公告)日：1996-08-06

申请号：US227315

申请日：1994-04-13

Applicant: Scott C. Sommerfeldt ,  Thomas W. Rudwick, III ,  Robert F. Miracky

Inventor： Scott C. Sommerfeldt ,  Thomas W. Rudwick, III ,  Robert F. Miracky

IPC: H01L23/538 ,  H05K1/00 ,  H05K3/46 ,  H05K1/11

CPC classification number: H01L23/5382 ,  H05K1/0287 ,  H05K1/029 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K1/0298 ,  H05K2201/09345 ,  H05K2201/09945 ,  H05K2203/175 ,  H05K3/467

Abstract: Provided is an electrical interconnect cell intermittently spaced across a substrate to form an interconnect device or structure. The interconnect device is fully customizable or programmable upon the upper surface to accommodate various electrical components and connectivity to those components. The electrical interconnect device includes a plurality of intermittently spaced first pairs of upper and lower signal lines interwoven with a plurality of intermittently spaced second pairs of upper and lower signal lines. A bonding pad is arranged between adjacent upper and lower signal line pairs and can be connected thereto with conductive links placed upon the surface layer. Each bonding pad includes one or more pad vias which extend perpendicular to the upper surface to conductive structures arranged in lower layers. Approximately one-half of the array of bonding pads are connected to potential conductors. The pairs of upper signal lines can not only be linked, but also can be cut to form a more direct routing between target locations. Moreover, the upper and lower signal lines are connected in order for traces to extend across the entire interconnect structure for ease of testability.

Abstract translation: 提供了间隔地跨越衬底以形成互连装置或结构的电互连电池。 互连设备在上表面上是完全可定制的或可编程的，以适应各种电气部件和与这些部件的连接。 电互连装置包括多个间歇间隔的第一对上，下信号线，与多个间歇间隔的第二对上，下信号线交织。 接合焊盘布置在相邻的上部和下部信号线对之间，并且可以与放置在表面层上的导电连接件连接。 每个焊盘包括一个或多个衬垫通孔，其垂直于上表面延伸到布置在较低层中的导电结构。 大约一半的焊盘阵列连接到电位导体。 上层信号线对不仅可以链接，而且可以被切割，以在目标位置之间形成更直接的路由。 此外，上下信号线被连接以使得迹线在整个互连结构上延伸以便易于测试。