公开(公告)号：US08138609B2

公开(公告)日：2012-03-20

申请号：US12832177

申请日：2010-07-08

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract translation: 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US20110095433A1

公开(公告)日：2011-04-28

申请号：US12908943

申请日：2010-10-21

Applicant: Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Tsuyoshi KOBAYASHI ,  Tatsuaki DENDA

Inventor： Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Tsuyoshi KOBAYASHI ,  Tatsuaki DENDA

IPC: H01L23/535 ,  H05K1/02 ,  H01L21/768 ,  B05D5/12

CPC classification number: H05K3/323 ,  H01L24/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/0315 ,  H05K2203/1142 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: There is provided a method of manufacturing a conductive film. The method includes: (a) providing an anodized layer having a plurality of through holes extending therethrough in its thickness direction; (b) forming a plurality of linear conductors by filling each of the through holes with a conductive material; (c) forming protection layers on both surfaces of the anodized layer; (d) removing the anodized layer to form a plurality of gaps between the linear conductors; (e) forming an organic insulation layer between the protection layers to fill the gaps with the organic insulation layer; and (f) removing the protection layers.

Abstract translation: 提供了一种制造导电膜的方法。 该方法包括：（a）提供阳极氧化层，其具有在其厚度方向上延伸穿过其中的多个通孔; （b）通过用导电材料填充每个所述通孔来形成多个线性导体; （c）在阳极氧化层的两个表面上形成保护层; （d）去除所述阳极化层以在所述线状导体之间形成多个间隙; （e）在保护层之间形成有机绝缘层，以用有机绝缘层填充间隙; 和（f）去除保护层。

公开(公告)号：US20110013406A1

公开(公告)日：2011-01-20

申请号：US12504627

申请日：2009-07-16

Applicant: Hsiao-Wan KUO

Inventor： Hsiao-Wan KUO

IPC: F21V21/00

CPC classification number: H05K1/142 ,  H05K1/0266 ,  H05K1/0287 ,  H05K3/0052 ,  H05K2201/09936 ,  H05K2201/09945 ,  H05K2201/10106 ,  H05K2201/10287

Abstract: The present invention provides a light emitting diode (LED) circuit board with a multi-directional electrical connection. The board includes a board body with a surface and an assembly plane as well as four sides and corresponding corners, and a plurality of positive and negative electric contacts, separately arranged onto the surface of the board body nearby four sides, and also arranged at intervals. The circuit of the LED circuit board is simplified, helping to facilitate multi-directional electrical connection and expansion, and to improve significantly the paving efficiency of the LED circuit board with better practicability and industrial benefits.

Abstract translation: 本发明提供一种具有多方向电连接的发光二极管（LED）电路板。 板包括具有表面和组装平面以及四个侧面和相应角部的板体，以及分别布置在四个侧面附近的板体表面上的多个正负电触点，并且还间隔地布置 。 LED电路板的电路简化，有助于促进多方向电连接和扩展，并显着提高LED电路板的铺路效率，具有更好的实用性和工业效益。

公开(公告)号：US07516542B2

公开(公告)日：2009-04-14

申请号：US11254312

申请日：2005-10-19

Applicant: Koji Temba

Inventor： Koji Temba

IPC: H05K3/36

CPC classification number: H01L21/485 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0289 ,  H05K3/328 ,  H05K2201/09681 ,  H05K2201/09945 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring board is manufactured by a step of forming a meshy cylindrical body, where plural conductive rings are connected to each other at plural positions in the respective peripheral direction, a step of forming laminated meshy sheets, by squashing the meshy cylindrical body in the radial direction, a step of inserting an insulation sheet between the meshy sheets, and a step of forming lacking portions at a position in the peripheral direction of conductive rings of the meshy sheets. It becomes possible to directly join a semiconductor chip to the conductive ring of the meshy sheet, and therefore, a wiring circuit can be obtained without using a solder joint.

Abstract translation: 通过形成网状圆柱体的步骤制造布线板，其中多个导电环在各个周向的多个位置处彼此连接，通过在径向上挤压网状圆柱体而形成叠层网状片的步骤 方向，在网状片材之间插入绝缘片的步骤，以及在网状片材的导电环的周向的位置处形成缺损部分的步骤。 可以将半导体芯片直接接合到网状片的导电环上，因此可以在不使用焊点的情况下获得布线电路。

公开(公告)号：US20070246516A1

公开(公告)日：2007-10-25

申请号：US11409242

申请日：2006-04-21

Applicant: Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

Inventor： Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

IPC: B23K31/02 ,  B23K1/08

CPC classification number: B23K3/0638 ,  B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3478 ,  H05K3/3484 ,  H05K2201/09945 ,  H05K2203/0113 ,  H05K2203/043 ,  H01L2924/00

Abstract: A system, method, and device for applying conductive bonding material to a substrate are disclosed. The method includes providing conductive bonding material in a plurality of cavities of a mold. A total number of cavities in the plurality of cavities being greater than a total number of at least one conductive pad of a circuit supporting substrate corresponding to the mold. The conductive bonding material in the mold is heated to a reflow temperature of the conductive bonding material. At least one wettable surface is placed in substantial contact with the heated conductive bonding material in at least one cavity. The mold and the corresponding circuit supporting substrate are brought in close proximity to each other such that the heated conductive bonding material in at least one cavity comes in contact with at least one conductive pad of the corresponding circuit supporting substrate.

Abstract translation: 公开了一种用于将导电接合材料施加到基底的系统，方法和装置。 该方法包括在模具的多个空腔中提供导电接合材料。 多个空腔中的空腔的总数大于对应于模具的电路支撑衬底的至少一个导电焊盘的总数。 将模具中的导电接合材料加热至导电接合材料的回流温度。 在至少一个空腔中至少一个可润湿表面被放置成与被加热的导电接合材料基本接触。 模具和相应的电路支撑衬底彼此靠近，使得至少一个空腔中的加热的导电接合材料与相应的电路支撑衬底的至少一个导电焊盘接触。

公开(公告)号：US20060091544A1

公开(公告)日：2006-05-04

申请号：US11254312

申请日：2005-10-19

Applicant: Koji Temba

Inventor： Koji Temba

IPC: H01L23/48

CPC classification number: H01L21/485 ,  H01L23/5382 ,  H01L2924/0002 ,  H05K1/0287 ,  H05K1/0289 ,  H05K3/328 ,  H05K2201/09681 ,  H05K2201/09945 ,  H05K2203/175 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring board is manufactured by a step of forming a meshy cylindrical body, where plural conductive rings are connected to each other at plural positions in the respective peripheral direction, a step of forming laminated meshy sheets, by squashing the meshy cylindrical body in the radial direction, a step of inserting an insulation sheet between the meshy sheets, and a step of forming lacking portions at a position in the peripheral direction of conductive rings of the meshy sheets. It becomes possible to directly join a semiconductor chip to the conductive ring of the meshy sheet, and therefore, a wiring circuit can be obtained without using a solder joint.

公开(公告)号：US20030178221A1

公开(公告)日：2003-09-25

申请号：US10369793

申请日：2003-02-20

Inventor： Cindy Chia-Wen Chiu ,  Hsiao Ken Chuang

IPC: H01B007/00

CPC classification number: H01B1/22 ,  H05K3/323 ,  H05K2201/0129 ,  H05K2201/0133 ,  H05K2201/0195 ,  H05K2201/09945 ,  H05K2201/10234

Abstract: An anisotropically conductive structure for providing electrical interconnection between electronic components, and the process for making such anisotropically conductive structure. The anisotropically conductive structure includes a dielectric matrix having a substantially uniform thickness; and a plurality of conductive elements embedded in the dielectric matrix.

Abstract translation: 用于提供电子部件之间的电互连的各向异性导电结构以及制造这种各向异性导电结构的方法。 各向异性导电结构包括具有基本上均匀厚度的介电矩阵; 以及嵌入介质矩阵中的多个导电元件。

公开(公告)号：US06180226B2

公开(公告)日：2001-01-30

申请号：US09043879

申请日：1998-03-31

Applicant: Ciaran B. McArdle ,  Joseph Burke ,  Edward K. Welch, II

Inventor： Ciaran B. McArdle ,  Joseph Burke ,  Edward K. Welch, II

IPC: B32B900

CPC classification number: H05K3/323 ,  G03F7/34 ,  H01L2224/293 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01R4/04 ,  H05K2201/083 ,  H05K2201/09945 ,  H05K2203/0769 ,  H05K2203/104 ,  Y10T428/26 ,  H01L2924/00

Abstract: The present invention provides a number of interrelated methods for the production of random and ordered arrays of particles and recesses as well as films containing such arrays and recesses. The present invention also relates to the random and ordered arrays of particles and films prepared therefrom. The ordered arrays are obtained by the use of ferrofluid compositions which may be curable, solidifiable on non-curing/non-solidifiable. The arrays and films may contain electrically-conductive particles useful in electronic applications for effecting contact between leads or pads.

Abstract translation: 本发明提供了许多用于制造颗粒和凹槽的随机和有序阵列以及包含这种阵列和凹槽的膜的相关方法。 本发明还涉及由其制备的颗粒和膜的随机和有序阵列。 有序阵列通过使用铁固化/非固化的可固化，可固化的铁磁流体组合物获得。 阵列和膜可以包含用于电子应用中用于实现引线或焊盘之间的接触的导电颗粒。

公开(公告)号：US6126063A

公开(公告)日：2000-10-03

申请号：US911515

申请日：1997-08-14

Applicant: Sutee Vongfuangfoo ,  Minh Vuong ,  Brent R. Bacher

Inventor： Sutee Vongfuangfoo ,  Minh Vuong ,  Brent R. Bacher

IPC: B23K3/06 ,  H01L21/48 ,  H05K3/34 ,  B23K1/00

CPC classification number: H05K3/3478 ,  B23K3/0638 ,  H01L21/4853 ,  H05K2201/09945 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/041

Abstract: Apparatus and method for assembling solder balls in a selected one of several different patterns for delivery to connector pads on an integrated circuit package, or other receiver, includes a universal template containing holes at locations in an aggregate pattern of all hole locations for the several different patterns, and includes a subtemplate for each individual different pattern that contains posts at locations for insertion from the rear of the template into holes therein at locations where no surface recess is desired. The universal template may remain aligned with an assembly jig or holder of packages while only the subtemplate is changed to change the surface pattern of holes into which solder balls may then be distributed.

Abstract translation: 用于组装多个不同图案中所选择的一种中的焊球的装置和方法用于传送到集成电路封装或其它接收器上的连接器焊盘，其包括通用模板，其在位于所述多个不同位置的所有孔位置的集合图案中的位置处 并且包括用于每个单独不同图案的子模板，其在位置处的位置处用于从模板的后部插入到其中不需要表面凹槽的位置处的孔中。 通用模板可以与组装夹具或包装保持器保持一致，而仅改变子模板以改变可以分布焊料球的孔的表面图案。

公开(公告)号：US5910354A

公开(公告)日：1999-06-08

申请号：US810846

申请日：1997-03-04

Applicant: Carmine G. Meola ,  Daniel D. Johnson ,  Donald R. Banks ,  Joseph G. Ameen

Inventor： Carmine G. Meola ,  Daniel D. Johnson ,  Donald R. Banks ,  Joseph G. Ameen

IPC: H01R11/01 ,  H01B1/22 ,  H01L23/14 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/40 ,  B32B27/14 ,  H05K1/00

CPC classification number: H05K3/3436 ,  H01L23/145 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K3/4038 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T428/24826 ,  Y10T428/249958 ,  Y10T428/31544

Abstract: A metallurgical interconnect composite is provided defined by a compliant, metallurgical, open cell, porous substrate which has a plurality of Z-axis conductive pathways extending from one side of the substrate to the other side. Each conductive pathway terminates in a solder covered surface area.

Abstract translation: 冶金互连复合材料由柔性，冶金，开孔，多孔基材提供，其具有从基板的一侧延伸到另一侧的多个Z轴导电通路。 每个导电通路终止于焊料覆盖的表面积。