公开(公告)号：US07592202B2

公开(公告)日：2009-09-22

申请号：US11395021

申请日：2006-03-31

Applicant: Munehiro Toyama ,  Charan Gurumurthy ,  Toshimi Kohmura

Inventor： Munehiro Toyama ,  Charan Gurumurthy ,  Toshimi Kohmura

IPC: H01L21/00

CPC classification number: H05K1/183 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.

Abstract translation: 本发明的实施例是减少设备之间的互连长度的技术。 在具有基板表面的基板中形成空腔。 空腔有一个深度。 具有器件表面和厚度的第一器件被放置在腔中。 厚度与深度匹配，使得器件表面与衬底表面近似平面。 第一设备通过第二设备上的凸块附接到第二设备。

公开(公告)号：US20090217519A1

公开(公告)日：2009-09-03

申请号：US12279483

申请日：2007-02-15

Applicant: Bruno Lefevre ,  Christian Schwartz ,  Jean-Yves Moreno

Inventor： Bruno Lefevre ,  Christian Schwartz ,  Jean-Yves Moreno

IPC: H05K3/34

CPC classification number: H05K13/00 ,  B23K3/047 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10848 ,  H05K2203/1115 ,  H05K2203/1476 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174

Abstract: The invention relates to a method for producing an electronic module (2) comprising a printed circuit (4) board (3), at least one first type of component (5), and a second type of component (6), said method comprising the following steps: solder (8) is placed on the board; the first type of component is placed in position; the board is generally heated in order to melt the solder in such a way as to solder the first type of component; the second type of component is positioned in such a way that it has tongues (7) which are supported on the board by means of solder; and the solder is locally heated such that it melts in order to solder the second type of component. The invention also relates to a production line for implementing said method.

Abstract translation: 本发明涉及一种用于制造电子模块（2）的方法，该电子模块（2）包括印刷电路板（4），至少一种第一类型的部件（5）和第二类型的部件（6），所述方法包括 以下步骤：将焊料（8）放在板上; 第一种类型的部件被放置就位; 板通常被加热以便熔化焊料，以便焊接第一类型的部件; 第二类型的部件被定位成使得其具有通过焊料支撑在板上的舌部（7）; 并且焊料被局部加热，使得其熔化以便焊接第二类型的部件。 本发明还涉及一种用于实现所述方法的生产线。

公开(公告)号：US20090175323A1

公开(公告)日：2009-07-09

申请号：US11970549

申请日：2008-01-08

Applicant: Woo Cheol Chung

Inventor： Woo Cheol Chung

IPC: H04B1/38

CPC classification number: H05K1/0243 ,  H01L23/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01Q1/2266 ,  H01Q1/521 ,  H01Q17/00 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/086 ,  H05K2201/10098 ,  H05K2201/10515 ,  H05K2201/10674

Abstract: Wireless chip-to-chip communications are methods and devices are disclosed. In an example, a wireless chip-to-chip communication device includes a plurality of chips, each of the plurality of chips having at least one antenna and formed on a multi-layered structure. The multi-layered structure includes first and second absorption layers. The first and second absorption layers are configured to enclose a propagation medium having a given dielectric constant. The plurality of chips are configured to wirelessly communicate with each other via the respective antennas in accordance with a given wireless communication protocol via a direct propagation path within the propagation medium.

Abstract translation: 无线芯片到芯片通信是公开的方法和设备。 在一个示例中，无线芯片到芯片通信设备包括多个芯片，所述多个芯片中的每一个具有至少一个天线并且以多层结构形成。 多层结构包括第一和第二吸收层。 第一和第二吸收层被配置为包围具有给定介电常数的传播介质。 多个芯片被配置为经由相应的天线根据给定的无线通信协议通过传播介质内的直接传播路径彼此无线地进行通信。

公开(公告)号：US20090166339A1

公开(公告)日：2009-07-02

申请号：US12279486

申请日：2007-02-15

Applicant: Bruno Lefevre ,  Christian Schwartz ,  Jean-Yves Moreno

Inventor： Bruno Lefevre ,  Christian Schwartz ,  Jean-Yves Moreno

IPC: B23K31/02 ,  B23K1/00

CPC classification number: H05K13/00 ,  B23K3/047 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/3494 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10848 ,  H05K2203/1115 ,  H05K2203/1476 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174

Abstract: The invention relates to a method for producing an electronic module (2) comprising a printed circuit (4) board (3), at least one first type of component (5), and a second type of component (6), said method comprising the following steps: solder is placed on the board; the first type of component is positioned; the solder is melted in order to solder the first type of component; the second type of component is positioned in such a way that it extends above the first type of component and has tongues (7) supported on the board by means of solder; and the solder is melted in order to solder the second type of component.

Abstract translation: 本发明涉及一种用于制造电子模块（2）的方法，该电子模块（2）包括印刷电路板（4），至少一种第一类型的部件（5）和第二类型的部件（6），所述方法包括 以下步骤：将焊料放在板上; 定位第一种类型的部件; 焊料熔化以便焊接第一类型的部件; 第二类型的部件被定位成使得其在第一类型的部件上方延伸并且具有通过焊料支撑在板上的舌部（7）; 并且焊料熔化以便焊接第二类型的部件。

公开(公告)号：US20090146301A1

公开(公告)日：2009-06-11

申请号：US12331467

申请日：2008-12-10

Applicant: Yoshiaki Shimizu ,  Yuichiro Yamada ,  Toshiyuki Fukuda

Inventor： Yoshiaki Shimizu ,  Yuichiro Yamada ,  Toshiyuki Fukuda

IPC: H01L23/482 ,  H01L23/488 ,  H01L21/44

CPC classification number: H05K3/38 ,  B29C43/18 ,  B29C45/02 ,  B29C45/14655 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/3511 ,  H05K3/3457 ,  H05K2201/0379 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/0278 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00012 ,  H01L2924/0695

Abstract: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the front face of a molding resin portion 10. The distal end of the protruding portion is a flat face 13. In addition, a portion of the projected electrode 9 whose cross section is larger than the protruding portion is positioned inside the molding resin portion 10.

Abstract translation: 提供能够实现高度可靠的三维安装的半导体器件及其制造方法。 突起电极9形成在基板5的元件安装区域的外侧的区域中。突出电极9包括从模制树脂部分10的前表面突出的突出部分。突出部分的远端是 另外，突出电极9的横截面大于突出部分的部分位于模制树脂部分10的内部。

公开(公告)号：US07531416B2

公开(公告)日：2009-05-12

申请号：US11313562

申请日：2005-12-21

Applicant: Daniel Irwin Amey, Jr. ,  William J. Borland

Inventor： Daniel Irwin Amey, Jr. ,  William J. Borland

IPC: H01L21/8222

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/50 ,  H01L23/66 ,  H01L27/013 ,  H01L2924/0002 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.

Abstract translation: 在具有高电容密度和其它所需电气和物理特性的陶瓷互连基板上形成厚膜电容器。 电容器电介质在高温下烧制。

公开(公告)号：US07521788B2

公开(公告)日：2009-04-21

申请号：US11233078

申请日：2005-09-23

Applicant: Hyo-Jae Bang ,  Byung-Man Kim ,  Dong-Chun Lee ,  Kwang-Su Yu

Inventor： Hyo-Jae Bang ,  Byung-Man Kim ,  Dong-Chun Lee ,  Kwang-Su Yu

IPC: H01L23/48 ,  H01L21/00 ,  H05K1/14 ,  H01R12/00

CPC classification number: H05K3/325 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/3511 ,  H05K2201/0314 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor module and a method of manufacturing a semiconductor module including at least one chip package, at least one module board, at least one conductive element provided between the first chip package and the module board and a protector for applying pressure to the conductive element, the module board, and the first chip package and/or acting as a heat sink for the first chip package.

Abstract translation: 一种半导体模块和半导体模块的制造方法，所述半导体模块包括至少一个芯片封装，至少一个模块板，设置在所述第一芯片封装和所述模块板之间的至少一个导电元件和用于向所述导电元件施加压力的保护器， 模块板和第一芯片封装和/或用作第一芯片封装的散热器。

公开(公告)号：US20090091022A1

公开(公告)日：2009-04-09

申请号：US11869211

申请日：2007-10-09

Applicant: Thorsten Meyer ,  Markus Brunnbauer ,  Jens Pohl

Inventor： Thorsten Meyer ,  Markus Brunnbauer ,  Jens Pohl

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/185 ,  H05K2201/09118 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/1316 ,  H05K2203/1469 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.

Abstract translation: 公开了一种制造器件，半导体芯片封装和半导体芯片组件的方法。 一个实施例包括在第一成形元件上施加至少一个半导体芯片。 至少一个元素被应用在第二个表单元素上。 在至少一个半导体芯片上和该至少一个元件上施加材料。

公开(公告)号：US07514636B2

公开(公告)日：2009-04-07

申请号：US11290314

申请日：2005-11-29

Applicant: Yorihiko Sasaki

Inventor： Yorihiko Sasaki

IPC: H05K1/00

CPC classification number: H01L23/4334 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49575 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/0207 ,  H05K1/187 ,  H05K3/205 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A circuit component module includes a heat-releasing plate, a resin film stacked on a surface of the heat-releasing plate, an electronic component embedded in the first resin film and partially in contact with the heat-releasing plate, and a wiring pattern embedded in the surface of the first resin film opposite the heat-releasing plate. The wiring pattern forms a circuit in combination with the electronic component.

Abstract translation: 电路部件模块包括散热板，层叠在散热板的表面上的树脂膜，嵌入在第一树脂膜中并部分地与散热板接触的电子部件，以及嵌入了布线图案 在第一树脂膜的与散热板相对的表面上。 布线图形与电子部件组合形成电路。

公开(公告)号：US07508070B2

公开(公告)日：2009-03-24

申请号：US11623075

申请日：2007-01-13

Applicant: Cheng-Lien Chiang

Inventor： Cheng-Lien Chiang

IPC: H01L23/34 ,  H01L23/02

CPC classification number: H01L25/105 ,  H01L25/18 ,  H01L2225/1005 ,  H01L2924/0002 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A two dimensional stacking structure for integrated chip stacking on a printed circuit board having a controller electrically coupling on the printed circuit board, comprising a first integrated circuit package, a second integrated circuit package and two interposers. The first integrated circuit package is located beside the controller and electrically coupled on the printed circuit board, and has first leads. The second integrated circuit package is located on the controller, and has second leads. The two interposers having first metal contacts attaching to the corresponding first leads, second metal contacts attaching to the corresponding second leads, and circuit traces extending from the first metal contacts to the corresponding second metal contacts providing electrical communication between the first integrated circuit package and the second integrated package. The two dimensional stacking structure may be applied to a circuit module to decrease the profile of the circuit module.

Abstract translation: 一种用于在印刷电路板上集成芯片堆叠的二维堆叠结构，其具有电连接在印刷电路板上的控制器，包括第一集成电路封装，第二集成电路封装和两个插入件。 第一个集成电路封装位于控制器旁边，并电连接在印刷电路板上，并具有第一引线。 第二个集成电路封装位于控制器上，并具有第二个引线。 所述两个插入件具有附接到相应的第一引线的第一金属触点，附接到对应的第二引线的第二金属触点和从第一金属触点延伸到相应的第二金属触点的电路迹线，从而提供第一集成电路封装和 第二个集成包。 二维堆叠结构可以应用于电路模块以减小电路模块的轮廓。