公开(公告)号：US10534719B2

公开(公告)日：2020-01-14

申请号：US15819328

申请日：2017-11-21

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Roxana Rusitoru ,  Curtis Glenn Dunham

IPC: G06F12/1009 ,  G06F12/0802 ,  G06F12/06 ,  G06F12/0862 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F12/1036

Abstract: A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.

公开(公告)号：US20190384722A1

公开(公告)日：2019-12-19

申请号：US16007027

申请日：2018-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Arkaprava Basu ,  Michael LeBeane ,  Eric Van Tassell

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/50 ,  G06F9/48 ,  G06F13/16 ,  G06F13/22

Abstract: A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

公开(公告)号：US10467151B2

公开(公告)日：2019-11-05

申请号：US15695745

申请日：2017-09-05

Applicant: NGINX, Inc.

Inventor： Igor Sysoev ,  Valentin Bartenev ,  Nikolay Shadrin ,  Maxim Romanov

IPC: G06F12/00 ,  G06F12/1036 ,  G06F12/1009

Abstract: Data is dynamically shared from a first process to a second process by creating a shared memory segment, obtaining a file descriptor referencing the shared memory segment, and mapping the shared memory segment in an address space of a first process. The file descriptor is sent to a second process. Responsive to receiving the file descriptor, the shared memory segment is mapped in an address space of the second process. Via the shared memory segment, data from the first process is shared to the second process.

公开(公告)号：US20190303301A1

公开(公告)日：2019-10-03

申请号：US16447258

申请日：2019-06-20

Applicant: International Business Machines Corporation

Inventor： Dan F. GREINER ,  Charles W. GAINEY, Jr. ,  Lisa C. HELLER ,  Damian L. OSISEK ,  Erwin PFEFFER ,  Timothy J. SLEGEL ,  Charles F. WEBB

IPC: G06F12/1027 ,  G06F12/14 ,  G06F12/02 ,  G06F12/1036 ,  G06F9/30 ,  G06F12/1009

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

公开(公告)号：US10423537B2

公开(公告)日：2019-09-24

申请号：US15884526

申请日：2018-01-31

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Matthew Lucien Evans

IPC: G06F12/10 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/1036 ,  G06F12/02

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

公开(公告)号：US10394707B2

公开(公告)日：2019-08-27

申请号：US15527620

申请日：2014-11-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Mitchel E. Wright ,  Michael R Krause ,  Melvin K. Benedict ,  Dwight L. Barron

IPC: G06F11/20 ,  G06F12/02 ,  G06F12/10 ,  G06F13/28 ,  G06T11/60 ,  G11C16/10 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/1036

Abstract: In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.

公开(公告)号：US10380032B2

公开(公告)日：2019-08-13

申请号：US15454243

申请日：2017-03-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe Brandt ,  Markus Helms ,  Christian Jacobi ,  Markus Kaltenbach ,  Thomas Koehler ,  Frank Lehnert

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F9/455

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20190236025A1

公开(公告)日：2019-08-01

申请号：US16377556

申请日：2019-04-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US10324857B2

公开(公告)日：2019-06-18

申请号：US15416549

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1027

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

公开(公告)号：US20190155683A1

公开(公告)日：2019-05-23

申请号：US16238862

申请日：2019-01-03

Applicant: International Business Machines Corporation

Inventor： Lakshminarayana B. Arimilli ,  Richard L. Arndt ,  Bartholomew Blaner

IPC: G06F11/10 ,  G06F13/16 ,  G06F13/40 ,  G06F9/455 ,  G06F12/1036

Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.