公开(公告)号：US06566612B2

公开(公告)日：2003-05-20

申请号：US10055294

申请日：2002-01-22

Applicant: Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

Inventor： Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

IPC: H01R909

CPC classification number: H01L21/563 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.

公开(公告)号：US06534863B2

公开(公告)日：2003-03-18

申请号：US09781121

申请日：2001-02-09

Applicant: George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

Inventor： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC: H01L2348

CPC classification number: H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

公开(公告)号：US06426241B1

公开(公告)日：2002-07-30

申请号：US09439112

申请日：1999-11-12

Applicant: Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

Inventor： Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

IPC: H01L2144

CPC classification number: H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H05K3/101 ,  H05K3/107 ,  H05K3/3421 ,  H05K2201/0305 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2203/128 ,  H01L2924/00

Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

Abstract translation: 提供了一种用于在基板中形成三维电路的方法，用于形成导电迹线和通孔触点。 在该方法中，首先提供由基本绝缘材料形成的基板，然后形成在基板的顶表面中的沟槽和孔，然后用导电材料（例如焊料）填充凹槽和孔。 该方法可以以低成本进行，以通过使用注射成型焊接技术或熔融焊料筛选技术来填充槽和孔来产生高质量的电路基板。 衬底中的凹槽和孔可以通过各种技术形成，例如化学蚀刻，物理加工和热冲压。

公开(公告)号：US06341418B1

公开(公告)日：2002-01-29

申请号：US09301890

申请日：1999-04-29

Applicant: Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

Inventor： Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

IPC: H05K334

CPC classification number: H01L21/563 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.

Abstract translation: 公开了一种通过使用焊料凸块和底部填充层将半导体芯片直接贴合到电路板的方法。 在该方法中，首先在半导体芯片的顶表面上丝网印刷一层原位聚合物模材料，暴露出多个接合焊盘。 原位聚合物模具层形成有多个孔，然后在熔融焊料筛选过程中用焊料材料填充以形成焊料凸块。 然后将薄的含有焊剂的底层填充材料层放置在电路板的顶部上，该多个导电焊盘以镜像形式布置在半导体芯片上的接合焊盘上。 然后将半导体芯片和电路板与其中的底部填充层一起压在一起，并被加热到高于焊料材料的熔融温度的回流温度，直到在焊盘和导电焊盘之间建立电连通。 在粘合组件中，原位聚合物模层和底部填充材料层形成复合底层填料，以代替在耗时的过程中必须通过毛细管作用在粘合的芯片和衬底之间注入的常规底部填充材料。

公开(公告)号：US5982038A

公开(公告)日：1999-11-09

申请号：US850092

申请日：1997-05-01

Applicant: Hilton T. Toy ,  Lannie R. Bolde ,  James H. Covell, II ,  David L. Edwards ,  Lewis S. Goldmann ,  Peter A. Gruber

Inventor： Hilton T. Toy ,  Lannie R. Bolde ,  James H. Covell, II ,  David L. Edwards ,  Lewis S. Goldmann ,  Peter A. Gruber

IPC: H01L23/02 ,  H01L23/10 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/10 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/16152

Abstract: The present invention relates generally to a new scheme of providing a seal for semi-conductor substrates and chip carriers. More particularly, the invention encompasses a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection.For the preferred embodiment the multi-layer metallic seal is a two layer, solder structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder structure has a thick high melting point temperature region that is attached to a cap, and a thin interconnecting region of lower melting point temperature region for sealing the substrate to the cap.

Abstract translation: 本发明一般涉及为半导体衬底和芯片载体提供密封的新方案。 更具体地，本发明包括使用多层金属密封件来为芯片载体上的芯片提供保护的结构和方法。 这种多层金属密封提供增强的气密寿命和环境保护。 对于优选实施例，多层金属密封件是用于为模块产生低成本，高可靠性气密密封的两层焊料结构。 这种焊料结构具有连接到盖的厚的高熔点温度区域和用于将衬底密封到帽的较低熔点温度区域的薄互连区域。

公开(公告)号：US5821161A

公开(公告)日：1998-10-13

申请号：US850091

申请日：1997-05-01

Applicant: James H. Covell, II ,  Lannie R. Bolde ,  David L. Edwards ,  Lewis S. Goldmann ,  Peter A. Gruber ,  Hilton T. Toy

Inventor： James H. Covell, II ,  Lannie R. Bolde ,  David L. Edwards ,  Lewis S. Goldmann ,  Peter A. Gruber ,  Hilton T. Toy

IPC: H01L21/50 ,  H01L23/10 ,  H01L21/44

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/163

Abstract: The present invention relates generally to a new scheme of providing a seal for semi-conductor substrates and chip carriers. More particularly, the invention encompasses a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal is a two layer, solder structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder structure has a thick high melting point temperature region that is attached to a cap, and a thin interconnecting region of lower melting point temperature region for sealing the substrate to the cap.

Abstract translation: 本发明一般涉及为半导体衬底和芯片载体提供密封的新方案。 更具体地，本发明包括使用多层金属密封件来为芯片载体上的芯片提供保护的结构和方法。 这种多层金属密封提供增强的气密寿命和环境保护。 对于优选实施例，多层金属密封件是用于为模块产生低成本，高可靠性气密密封的两层焊料结构。 这种焊料结构具有连接到盖的厚的高熔点温度区域和用于将衬底密封到帽的较低熔点温度区域的薄互连区域。

公开(公告)号：US4730666A

公开(公告)日：1988-03-15

申请号：US858318

申请日：1986-04-30

Applicant: Ephraim B. Flint ,  Kurt R. Grebe ,  Peter A. Gruber ,  Arthur R. Zingher

Inventor： Ephraim B. Flint ,  Kurt R. Grebe ,  Peter A. Gruber ,  Arthur R. Zingher

IPC: H01L23/36 ,  H01L23/433 ,  H01L23/467 ,  F28F7/00 ,  H01R13/00

CPC classification number: H01L23/467 ,  F28F19/06 ,  F28F21/085 ,  F28F3/048 ,  H01L23/4338 ,  F28F2255/02 ,  F28F2255/14 ,  H01L2924/0002

Abstract: A heat exchanger for cooling an array of electric circuit chips disposed on a common substrate is formed as a flexible sheet of thermally conducting material with upstanding fins for transference of heat from the chips to a coolant flowing through the fins. The sheet may be provided with corrugations set between sites of the chips for improved flexibility to accommodate individual orientations of the chips. The sheet is sufficiently large to cover an array of chips and is secured adheringly, as by use of a thermally conductive grease, to the chips. The sheet hermetically seals the chips from contamination by the coolant. The heat exchanger may be fabricated of copper with a nickel coating, wherein the copper provides the heat conduction and the nickel protects the copper from a corrosive coolant such as water. The finned sheet may be efficiently fabricated by processes analogous to those used to make printed circuits. In one embodiment of the heat exchanger, the fin thickness, the fin spacing and the sheet thickness are all approximately equal, a typical sheet thickness being approximately two mils.

Abstract translation: 用于冷却设置在共同基板上的电路芯片的阵列的热交换器形成为具有用于将热从芯片传递到流过翅片的冷却剂的直立翅片的导热材料的柔性片。 片材可以设置在芯片的位置之间设置的波纹，以提高柔性以适应芯片的各个取向。 片材足够大以覆盖芯片阵列，并且通过使用导热油脂将密封件固定到芯片上。 片材气密地密封芯片以免受冷却剂的污染。 热交换器可以由具有镍涂层的铜制成，其中铜提供热传导，并且镍保护铜免受诸如水的腐蚀性冷却剂的影响。 翅片可以通过与用于制造印刷电路的那些类似的工艺被有效地制造。 在热交换器的一个实施例中，翅片厚度，翅片间距和片材厚度大致相等，典型的片材厚度约为2密耳。