公开(公告)号：US20220037322A1

公开(公告)日：2022-02-03

申请号：US17501914

申请日：2021-10-14

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11195944B2

公开(公告)日：2021-12-07

申请号：US15576508

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/78 ,  H01L21/762 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775

Abstract: Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor structures can be used for system-on-chip integration of high-voltage GaN front-end radio frequency (RF) switches on a bulk silicon substrate. The techniques can include, for example, forming multiple fins in a substrate, depositing the GaN layer on the fins, oxidizing at least a portion of each fin in a gap below the GaN layer, and forming one or more transistors on and/or from the GaN layer. In some cases, the GaN layer is a plurality of GaN islands, each island corresponding to a given fin. The techniques can be used to form various non-planar isolated GaN transistor architectures having a relatively small form factor, low on-state resistance, and low off-state leakage, in some cases.

公开(公告)号：US11183613B2

公开(公告)日：2021-11-23

申请号：US16643924

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L33/32 ,  H01L33/00 ,  H01L33/06 ,  H01L33/62

Abstract: Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure.

公开(公告)号：US11177376B2

公开(公告)日：2021-11-16

申请号：US16258422

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/06

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US20210210620A1

公开(公告)日：2021-07-08

申请号：US16081403

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Seung Hoon Sung ,  Robert B. Turkot ,  Marko Radosavljevic ,  Han Wui Then ,  Willy Rachmady ,  Sansaptak Dasgupta ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L21/3065

Abstract: The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.

公开(公告)号：US20200373297A1

公开(公告)日：2020-11-26

申请号：US16419240

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.

公开(公告)号：US10811526B2

公开(公告)日：2020-10-20

申请号：US16461353

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

公开(公告)号：US10804214B2

公开(公告)日：2020-10-13

申请号：US16302420

申请日：2016-06-27

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L29/66 ,  H01L23/552 ,  H01L23/66 ,  H01P3/00 ,  H01L23/522 ,  H01L21/8252 ,  H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01P11/00

Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).

公开(公告)号：US10777672B2

公开(公告)日：2020-09-15

申请号：US16084203

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L23/66 ,  H01L29/205 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08

Abstract: Embodiments of this disclosure are directed to a multi-gate gallium nitride (GaN) transistor and methods of making the same. The multi-gate GaN transistor includes a gallium nitride layer. The GaN transistor includes two or more gate electrodes between a drain electrode and a source electrode. A polarization layer is located between the first gate electrode and the second gate electrode, the polarization layer forming a two dimensional electron gas (2DEG) within the GaN layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode.

公开(公告)号：US10770575B2

公开(公告)日：2020-09-08

申请号：US16321722

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Pavel M. Agababov

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

Abstract: Vertical Group III-N devices and their methods of fabrication are described. In an example, a semiconductor structure includes a doped buffer layer above a substrate, and a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface. A drain region is disposed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region. A polarization charge inducing layer is disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the first portion of the polarization charge inducing layer.