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    Breaking out signals from an integrated circuit footprint
    131.
    发明授权
    Breaking out signals from an integrated circuit footprint 有权
    从集成电路占用空间中消除信号

    公开(公告)号：US06686666B2

    公开(公告)日：2004-02-03

    申请号：US10147800

    申请日：2002-05-16

    Applicant: Devadatta V. Bodas

    Inventor： Devadatta V. Bodas

    IPC: H01L2940

    CPC classification number: G06F17/5068 ,  H01L23/49838 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10734

    Abstract: Pads are arranged as an integrated circuit (IC) footprint, and are formed in a stackup that includes an insulating layer and multiple signal routing layers. The footprint has a polygonal shape. There is an inner pad region, a middle pad region that surrounds the inner pad region, and an outer pad region that surrounds the middle pad region. Some of the pads of each pad region are connected to a respective group of signal lines. Some of the signals that are connected to pads of the outer region which are located in a corner of the polygonal shape are routed out of the footprint in a different layer than the one used to route signal lines that are connected to pads of the outer region which are located between two adjacent corners of the polygonal shape.

    Abstract translation: 垫片被布置为集成电路（IC）占位面积，并且形成在堆叠中，其包括绝缘层和多个信号路由层。 足迹具有多边形。 内部衬垫区域，围绕内部衬垫区域的中间衬垫区域和围绕中间衬垫区域的外部衬垫区域。 每个焊盘区域的一些焊盘连接到相应的信号线组。 连接到位于多边形角落的外部区域的焊盘的一些信号以与用于路由连接到外部区域的焊盘的信号线的层不同的层布线 它们位于多边形形状的两个相邻角之间。

    Technique for reducing the number of layers in a signal routing device
    132.
    发明申请
    Technique for reducing the number of layers in a signal routing device 失效
    用于减少信号路由设备中的层数的技术

    公开(公告)号：US20040016117A1

    公开(公告)日：2004-01-29

    申请号：US10326123

    申请日：2002-12-23

    Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Guy A. Duxbury ,  Luigi G. Difilippo

    IPC: H01K003/10 ,  H01H001/00 ,  G01R001/00

    CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A technique for reducing the number of layers in a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing the number of layers in a multilayer signal routing device having a plurality of electrically conductive signal path layers for routing electrical signals to and from at least one electronic component mounted on a surface of the multilayer signal routing device. In such a case, the method comprises routing electrical signals on the plurality of electrically conductive signal path layers in the multilayer signal routing device for connection to and from a high density electrically conductive contact array package based at least in part upon at least one of an electrically conductive contact signal type characteristic and an electrically conductive contact signal direction characteristic.

    Abstract translation: 公开了一种用于减少多层信号路由设备中的层数的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于减少具有多个导电信号路径层的多层信号路由设备中的层数的方法，用于将电信号路由到至少一个安装在 多层信号路由设备的表面。 在这种情况下，该方法包括在多层信号路由设备中的多个导电信号路径层上布置电信号，用于至少部分地基于以下各项中的至少一个来连接至高密度导电触点阵列封装： 导电接触信号类型特性和导电接触信号方向特性。

    Semiconductor device having wide wiring pattern in outermost circuit
    134.
    发明申请
    Semiconductor device having wide wiring pattern in outermost circuit 有权
    在最外层电路中具有宽布线图案的半导体器件

    公开(公告)号：US20030159122A1

    公开(公告)日：2003-08-21

    申请号：US10291419

    申请日：2002-11-12

    Inventor： Taku Iida ,  Satoru Kawamoto ,  Toshiaki Yagura

    IPC: G06F017/50 ,  H03K017/693

    CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01068 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/10734

    Abstract: A semiconductor electronic part, having a lot of bumps allocated in a checkered pattern, is solder-mounted on a multilayer circuit board. In the multilayer circuit board, a first wiring pattern linked with a first land is finer than a second wiring pattern linked with a second land. Only one first wiring pattern is passable between lands. The second lands are allocated in the outmost line on the uppermost layer of the multilayer circuit board. In the semiconductor electronic part, bumps connectable with the second lands are allocated in the outermost line.

    Abstract translation: 具有以方格图案分配的大量凸块的半导体电子部件被焊接安装在多层电路板上。 在多层电路板中，与第一焊盘连接的第一布线图案比与第二焊盘连接的第二布线图案更细。 在陆地之间只能有一个第一个布线图案可以通过。 第二焊盘被分配在多层电路板的最上层的最外层。 在半导体电子部件中，与第二焊盘连接的凸块分配在最外面的线路中。

    Circuit pattern for multi-layer circuit board for mounting electronic parts
    137.
    发明授权
    Circuit pattern for multi-layer circuit board for mounting electronic parts 失效
    用于安装电子部件的多层电路板的电路图案

    公开(公告)号：US06452115B2

    公开(公告)日：2002-09-17

    申请号：US09781302

    申请日：2001-02-13

    Applicant: Michio Horiuchi ,  Eiji Yoda ,  Chiaki Takubo

    Inventor： Michio Horiuchi ,  Eiji Yoda ,  Chiaki Takubo

    IPC: H51R909

    CPC classification number: H05K1/112 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/10734

    Abstract: A multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many pins as 40×40 pins arranged as an array on the side of the mounting surface or a semiconductor device has a plurality of layers, each layer disposed one above another and containing lands arranged as an array disposed at an angle to the edge of the mounting surface. On each layer a plurality of the lands have connected thereto circuits extending from the lands to the edge of the mounting surface, and also lands not connected to circuits. Those lands not connected to circuits are connected with via holes to orther layers. The numbers (n−2) of lands and the position of lands connected to circuits on a layer is defined where n is the smallest integer that satisfies the equation m≧(k+1) wherein m={(land pitch)×(n−1)−(land diameter)−(space between patterns)}÷(pattern width+space between patterns) and k=&agr;(n−1)+(n−2).

    Abstract translation: 用于安装诸如半导体芯片的电子部件的多层电路板，具有作为阵列布置成安装面侧面的40×40引脚的半导体芯片或半导体器件的半导体芯片具有多层，每层设置在另一层上 并且包括布置成与安装表面的边缘成一定角度设置的阵列。 在每个层上，多个焊盘已经连接到从焊盘延伸到安装表面的边缘的电路，并且还没有连接到电路。 未连接到电路的那些焊盘与通孔连接到其他层。 定义了土地的数量（n-2）和连接到层上的电路的土地的位置，其中n是满足等式m> =（k + 1）的最小整数，其中

    Ball grid array semiconductor package structure to avoid high frequency interference
    138.
    发明申请
    Ball grid array semiconductor package structure to avoid high frequency interference 审中-公开
    球栅阵列半导体封装结构，避免高频干扰

    公开(公告)号：US20020125570A1

    公开(公告)日：2002-09-12

    申请号：US09800822

    申请日：2001-03-08

    Inventor： Yu-Chun Wu ,  Chi-Tsung Chiu ,  Li-Chuan Chang Chien ,  Yung-I Yeh

    IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40 ,  H01L023/528

    CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/0243 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09418 ,  Y02P70/613 ,  H01L2924/00

    Abstract: A BGA semiconductor package structure that is able to avoid high frequency interference has at least one non-ball mounting area on a bottom face of a substrate, wherein high frequency bump balls are mounted abreast on the non-ball mounting ball area. When the BGA package device is mounted on a PCB, the non-ball mounting area correspond the electric wires, such that the electric wires which are formed on the PCB are able to transmit high frequency signals and connect the high frequency bump balls. Thus, when the high frequency signals are transmitted via the electric wires, the high frequency signals do not affect other signals transmitted via other electric wires.

    Abstract translation: 能够避免高频干扰的BGA半导体封装结构在基板的底面上具有至少一个非球安装区域，其中高频凸块球并排安装在非球安装球区域上。 当BGA封装器件安装在PCB上时，非球安装区域对应于电线，使得形成在PCB上的电线能够传输高频信号并连接高频碰撞球。 因此，当通过电线传输高频信号时，高频信号不影响通过其他电线传输的其它信号。

    Printed circuit board having signal patterns of varying widths
    139.
    发明授权
    Printed circuit board having signal patterns of varying widths 失效
    具有不同宽度的信号图案的印刷电路板

    公开(公告)号：US06340797B1

    公开(公告)日：2002-01-22

    申请号：US09468295

    申请日：1999-12-21

    Applicant: Takashi Yoshida ,  Masahide Watanabe ,  Nobuo Taketomi

    Inventor： Takashi Yoshida ,  Masahide Watanabe ,  Nobuo Taketomi

    IPC: H05K116

    CPC classification number: H05K1/112 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/10734

    Abstract: A printed circuit board is provided with a plurality of insulator layers and a plurality of conductor layers, and an outermost conductor layer has a plurality of foot patterns in outer and inner rows for mounting a BGA component and signal patterns. The width of at least a part of the signal pattern extending from the foot pattern in the outer row is greater than the width of the signal pattern extending from the foot pattern in the inner row. The printed circuit board further includes a protection layer for covering the signal patterns on the outermost conductor layer, and the protection layer has openings each for permitting the foot pattern to be exposed. At least a portion of the signal pattern appearing in the opening is widened.

    Abstract translation: 印刷电路板设置有多个绝缘体层和多个导体层，并且最外面的导体层具有用于安装BGA部件和信号图案的外排和内排中的多个脚图案。 从外排中的脚图形延伸的信号图案的至少一部分的宽度大于从内排中的脚图案延伸的信号图案的宽度。 印刷电路板还包括用于覆盖最外面的导体层上的信号图案的保护层，并且保护层具有各自的开口以允许脚图案露出。 出现在开口中的信号图案的至少一部分变宽。

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