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公开(公告)号：US20200375484A1
公开(公告)日：2020-12-03
申请号：US16886714
申请日：2020-05-28
Applicant: IMEC VZW , Katholieke Universiteit Leuven , Stichting IMEC Nederland
Inventor： Qiuyang LIN , Jiawei XU , Shuang SONG , Nick VAN HELLEPUTTE , Filip TAVERNIER
Abstract: A light-to-digital converter (2) comprises a light-to-current converter (10); a current integrator (4) with an integrator output (30) resettable to a baseline level; and a counter (18) with a digital output (26), wherein the light-to-current converter (10) is switchably connectable as a positive integration input to the current integrator (4), for, during a light-collecting phase (404-406), integrating a current from the light-to-current converter (10), the integrator output (30) starting from the baseline value and ending at a value to be digitized; a reference current source (14) is switchably connectable as a negative integration input to the current integrator (4), for, during a counting phase (406-408) subsequent to the light-collecting phase (404-406), integrating a reference current from the reference current source (14), the integrator output (30) starting from the value to be digitized and ending at the baseline value, the time spent integrating the reference current corresponding to the value to be digitized; and the counter (18) is configured for measuring the time.
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公开(公告)号：US10819277B2
公开(公告)日：2020-10-27
申请号：US16527471
申请日：2019-07-31
Applicant: Stichting IMEC Nederland
Inventor： Cui Zhou , Paul Mateman
Abstract: A differential Colpitts oscillator circuit is described which provides a larger tuning range, has better phase noise and uses less power than conventional differential Colpitts oscillator circuits. The circuit is characterized by a capacitive ladder in which only variable capacitor is used for tuning the circuit. In some embodiments, a variable capacitor can be used for fine tuning.
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143.发明授权公开(公告)号：US10739802B2
公开(公告)日：2020-08-11
申请号：US16506331
申请日：2019-07-09
Applicant: STICHTING IMEC Nederland
Inventor： Stefano Stanzione
Abstract: A low dropout, LDO, voltage regulator comprising: an LDO input configured to receive an input voltage signal; an LDO output configured to output an output voltage signal; an error amplifying circuit, which is configured to receive a reference signal and a feedback signal associated with the output voltage signal, the error amplifying circuit being further configured to output an error signal; an output stage, which is configured to receive the error signal and output a control signal; and an output device, which is connected to the LDO input and configured to provide the output voltage signal and which is controlled by the control signal for regulating the output voltage signal; wherein the output stage is connected to the input voltage for receiving an adaptive bias current.
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公开(公告)号：USD888967S1
公开(公告)日：2020-06-30
申请号：US29635114
申请日：2018-01-29
Applicant: Stichting IMEC Nederland
Designer： Bernard Grundlehner , Shrishail Patki , Peter Cramer , Bastiaan Hemmes
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公开(公告)号：US10686464B2
公开(公告)日：2020-06-16
申请号：US16507875
申请日：2019-07-10
Applicant: STICHTING IMEC Nederland
Inventor： Roland Van Wegberg
Abstract: A latched comparator comprises a pre-amplifier stage with a positive input (Vin,p), a negative input (Vin,n); and a differential output (ΔVout) comprising a first output (Vout,1) and a second output (Vout,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (Vin,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (Vout,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (Vin,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (Vout,2); a first gain-boosting transistor (MN6) connected between the first output (Vout,1) and the first cascode node; and a second gain-boosting transistor (MN7) connected between the second output (Vout,2) and the second cascode node, wherein the first gain-boosting transistor (MN6) and the second gain-boosting transistor (MN7) are cross-coupled, so that the first gain-boosting transistor (MN6) is controlled by the second output (Vout,2) and the second gain-boosting transistor (MN7) is controlled by the first output (Vout,2).
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Patent Agency Ranking
公开(公告)号：US20200014392A1
公开(公告)日：2020-01-09
申请号：US16503690
申请日：2019-07-05
Applicant: Stichting IMEC Nederland
Inventor： XiaoYan Wang , Kia Salimi
Abstract: An example oscillator device comprises (i) an oscillation circuit arranged for generating and outputting an oscillation signal and comprising an active circuit to ensure oscillation is maintained, (ii) a voltage-to-current conversion replica circuit of the active circuit arranged for receiving the oscillation signal and for outputting a current proportional to the oscillation signal, (iii) biasing means arranged to generate a constant bias current to activate the oscillation circuit, and (iv) subtraction means for subtracting the current proportional to the oscillation signal from the bias current, thereby obtaining a resulting current which can be used for adapting the oscillation signal's amplitude.
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公开(公告)号：US20190204216A1
公开(公告)日：2019-07-04
申请号：US16200352
申请日：2018-11-26
Applicant: IMEC vzw , Stichting IMEC Nederland
Inventor： Peter Offermans , Joris Van Campenhout
CPC classification number: G01N21/3586 , G01J1/0407 , G01J1/44 , G01J3/0205 , G01J3/42 , G01J5/0818 , G01J5/0837 , G01J5/10 , G01J5/28 , G02B6/12 , G02B6/1228 , G02F2203/13 , H01L31/09
Abstract: A solid-state device for photo detection, in general, of terahertz radiation is disclosed. One aspect is a detector device comprising a body having a photoconductive material, a first antenna element connected to a first portion of the body, and a second antenna element connected to a second portion of the body. The first antenna element and the second antenna element are arranged to induce an electric field in the body in response to an incident signal. Further, the device has a waveguide arranged to couple light into the photoconductive material via a coupling interface between the waveguide and the body, where the coupling interface faces away from the first portion and the second portion of the body and is closer to the first portion than to the second portion.
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公开(公告)号：US10236894B2
公开(公告)日：2019-03-19
申请号：US15688513
申请日：2017-08-28
Applicant: Stichting IMEC Nederland
Inventor： Johan van den Heuvel , Yao-Hong Liu
Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.
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公开(公告)号：US10200047B2
公开(公告)日：2019-02-05
申请号：US15605261
申请日：2017-05-25
Applicant: IMEC VZW , Stichting IMEC Nederland , Vrije Universiteit Brussel
Inventor： Nereo Markulic , Yao-Hong Liu , Jan Craninckx
Abstract: The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a random offset, i.e. a pseudo-random integer, to the delay value. The offset is such that a target output of the phase detector remains substantially unchanged.
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公开(公告)号：US10191002B2
公开(公告)日：2019-01-29
申请号：US15202685
申请日：2016-07-06
Applicant: Stichting IMEC Nederland
Inventor： Daan Wouters
IPC: G01N27/06 , G01N27/02 , G01N27/404 , G01N27/22 , G01N33/00
Abstract: The present disclosure relates to methods and devices for gas sensing. A gas sensor includes a sensing element comprising at least an ionic liquid. The gas sensor also includes a set of electrodes for polarizing the sensing element and an electric power source for powering the set of electrodes, thus generating an impedimetric response signal from the sensing element. The gas sensor additionally includes readout circuitry for separately analyzing resistive and capacitive components in the impedimetric response signal. A method includes exposing a gas sensor to a gas. The gas sensor includes a sensing element including at least an ionic liquid. The method also includes polarizing the sensing element with an electrical signal at a first frequency, measuring an impedimetric response signal of the sensing element, separating the signal into resistive and capacitive components, and determining the composition of the gas based at least on the resistive and capacitive components.
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