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    Method of fabricating microchannel array structure embedded in silicon substrate
    142.
    发明授权
    Method of fabricating microchannel array structure embedded in silicon substrate 有权
    制造嵌入硅衬底的微通道阵列结构的方法

    公开(公告)号：US06582987B2

    公开(公告)日：2003-06-24

    申请号：US10022093

    申请日：2001-12-14

    Applicant: Chi Hoon Jun ,  Chang Auck Choi ,  Youn Tae Kim

    Inventor： Chi Hoon Jun ,  Chang Auck Choi ,  Youn Tae Kim

    IPC: H01L2100

    CPC classification number: B81C1/00119 ,  B81B2201/0214 ,  B81B2201/058

    Abstract: The present invention is disclosed a microchannel array structure embedded in a silicon substrate and a fabrication method thereof. The microchannel array structure of the present invention is formed deep inside the substrate and has high-density microscopic micro-channels. Besides, going through surface micromachining, physical and chemical properties of the silicon substrate are hardly influenced by the fabrication procedures. With microchannels buried in the substrate, the top of a microchannel array structure becomes flat, minimizing the effect of step height. That way, additional devices such as passive components, micro sensors, micro actuators and electronic devices can be easily integrated onto the microchannel array structure. The microchannel array structure of the present invention can be employed as a basic fluidic platform for miniaturizing and improving perfomances of electronic device coolers as well as such fluidic micro-electro-mechanical system (MEMS) devices as biochips, microfluidic components and chemical analyzers, lab-on-a-chips, polymerase chain reaction (PCR) amplifiers, micro reactors and drug delivery systems.

    Abstract translation: 本发明公开了一种嵌入硅衬底的微通道阵列结构及其制造方法。 本发明的微通道阵列结构形成在衬底的内部，并且具有高密度微观微通道。 此外，通过表面微加工，硅衬底的物理和化学性质几乎不受制造程序的影响。 由于微通道埋在基板中，微通道阵列结构的顶部变得平坦，从而最小化台阶高度的影响。 这样，诸如无源组件，微传感器，微执行器和电子设备的附加设备可以容易地集成到微通道阵列结构上。 本发明的微通道阵列结构可用作电子装置冷却器的微型化和改进的基本流体平台，以及诸如生物芯片，微流体组件和化学分析仪的实验室的这种流体微机电系统（MEMS）装置 - 聚合酶链反应（PCR）放大器，微反应器和药物递送系统。

    Adjustable nanopore, nanotome, and nanotweezer
    143.
    发明申请
    Adjustable nanopore, nanotome, and nanotweezer 失效
    可调节纳米孔，纳米切片机和纳米晶体管

    公开(公告)号：US20030080042A1

    公开(公告)日：2003-05-01

    申请号：US10022452

    申请日：2001-10-30

    Inventor： Philip W. Barth ,  Daniel B. Roitman ,  Joel Myerson

    IPC: B01D063/00

    CPC classification number: G01N33/48721 ,  B01D67/0058 ,  B01D67/0072 ,  B01D69/02 ,  B01D69/12 ,  B01D71/02 ,  B01D2325/02 ,  B81B3/0059 ,  B81B5/00 ,  B81B2201/0214 ,  B81B2201/047 ,  B81B2203/0353 ,  B81C99/002 ,  B82Y15/00 ,  B82Y30/00

    Abstract: An adjustable nanopore is fabricated by placing the surfaces of two planar substrates in contact, wherein each substrate contains a hole having sharp corners and edges. A corner is brought into proximity with an edge to define a triangular aperture of variable area. Ionic current in a liquid solution and through the aperture is monitored as the area of the aperture is adjusted by moving one planar substrate with respect to the other along two directional axes and a rotational axis. Piezoelectric positioners can provide subnanometer repeatability in the adjustment process. The invention is useful for characterizing, cleaving, and capturing molecules, molecular complexes, and supramolecular complexes which pass through the nanopore, and provides an improvement over previous devices in which the hole size of nanopores fabricated by etching and/or redeposition is fixed after fabrication.

    Abstract translation: 通过将两个平面基板的表面放置接触来制造可调纳米孔，其中每个基板包含具有锐角和边缘的孔。 一个角落靠近一个边缘以限定可变区域的三角形孔。 通过沿着两个方向轴和旋转轴线相对于另一个移动一个平面基板来调节在液体溶液中并通过孔的离子电流，因为孔的面积被调整。 压电定位器可以在调整过程中提供亚纳米计重复性。 本发明可用于表征，切割和捕获通过纳米孔的分子，分子复合物和超分子复合物，并且对先前的装置提供了改进，其中通过蚀刻和/或再沉积制造的纳米孔的孔径在制造后被固定 。

    Boron nutride membrane in wafer structure
    148.
    发明授权
    Boron nutride membrane in wafer structure 失效
    硼硅胶膜晶圆结构

    公开(公告)号：US5270125A

    公开(公告)日：1993-12-14

    申请号：US782705

    申请日：1991-10-25

    Applicant: William G. America ,  Richard R. Poole

    Inventor： William G. America ,  Richard R. Poole

    IPC: C23C16/34 ,  G01N25/18 ,  G03F1/22 ,  B32B9/00 ,  G03F9/00

    CPC classification number: B81B3/0021 ,  C23C16/342 ,  G01N25/18 ,  G03F1/22 ,  B81B2201/0214 ,  B81B2201/0278 ,  B81B2201/052 ,  B81B2201/054 ,  B81B2203/0127 ,  B81B2203/0315 ,  Y10T428/24612 ,  Y10T428/24777

    Abstract: A laminated structure includes a wafer member with a membrane attached thereto, the membrane being formed of substantially hydrogen-free boron nitride having a nominal composition B.sub.3 N. The structure may be a component in a mechanical device for effecting a mechanical function, or the membrane may form a masking layer on the wafer. The structure includes a body formed of at least two wafer members laminated together with a cavity formed therebetween, with the boron nitride membrane extending into the cavity so as to provide the structural component such as a support for a heating element or a membrane in a gas valve. In another aspect borom is selectively diffused from the boron nitride into a surface of a silicon wafer. The surface is then exposed to EDP etchant to which the diffusion layer is resistant, thereby forming a channel the wafer member with smooth walls for fluid flow.

    Abstract translation: 叠层结构包括具有膜的膜片构件，膜由具有标称组成B3N的基本上无氢的氮化硼形成。 该结构可以是用于实现机械功能的机械装置中的部件，或者膜可以在晶片上形成掩模层。 该结构包括由至少两个晶片构件形成的主体，所述至少两个晶片构件在其间形成有腔，其中氮化硼膜延伸到空腔中，以便提供结构部件，例如气体中的加热元件或膜的支撑体 阀。 在另一方面，硼化物选择性地从氮化硼扩散到硅晶片的<100>表面。 然后将表面暴露于扩散层所抵抗的EDP蚀刻剂，从而形成具有平滑壁用于流体流动的晶片构件的通道。

    METHOD FOR MANUFACTURING PACKAGE STRUCTURE
    150.
    发明公开
    METHOD FOR MANUFACTURING PACKAGE STRUCTURE 审中-公开

    公开(公告)号：US20240217808A1

    公开(公告)日：2024-07-04

    申请号：US18609571

    申请日：2024-03-19

    Applicant: Winbond Electronics Corp.

    Inventor： Jin-Neng WU

    IPC: B81B3/00 ,  B81C3/00

    CPC classification number: B81B3/0018 ,  B81C3/001 ,  B81B2201/0214 ,  B81B2201/03 ,  B81B2203/033 ,  B81B2207/09

    Abstract: A method for manufacturing package structure is provided, including: providing a substrate having recesses; forming first MEMS chips on the substrate, each with a through-substrate via, and a first sensor or microactuator on the lower surface, located in one of the recesses; forming first intermediate chips on the substrate, each respectively on one of the first MEMS chips, having a through-substrate via, and including a signal conversion unit, a logic operation unit, control unit, or a combination thereof; forming second MEMS chips on the first intermediate chips, each with a through-substrate via, having a second sensor or microactuator on its upper surface, wherein the package structure includes at least one of the first sensor and the second sensor; and forming first capping plates on the second MEMS chips, each providing a receiving space for the second sensor or microactuator on the upper surface of each second MEMS chip.

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