公开(公告)号：US09117697B2

公开(公告)日：2015-08-25

申请号：US14303371

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che Lee ,  Yuan-Chang Su ,  Wen-Chi Cheng ,  Guo-Cheng Liao ,  Yi-Chuan Ding

IPC: H01L23/52 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/11019 ,  H01L2224/11622 ,  H01L2224/1163 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/16225 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2203/0723 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.

Abstract translation: 本公开涉及一种半导体衬底及其制造方法。 半导体衬底包括绝缘层，第一电路层，第二电路层，多个导电通孔和多个凸块。 第一电路层嵌入绝缘层的第一表面，并从绝缘层的第一表面露出。 第二电路层位于绝缘层的第二表面上，并通过导电通孔与第一电路层电连接。 凸块直接位于第一电路层的一部分上，其中凸块的晶格与第一电路层的晶格相同。

公开(公告)号：US09029891B2

公开(公告)日：2015-05-12

申请号：US13749096

申请日：2013-01-24

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Shigetsugu Muramatsu ,  Hiroshi Shimizu ,  Kazutaka Kobayashi

IPC: H01L33/60 ,  H05K3/10 ,  H05K3/20 ,  H05K1/02 ,  H05K3/00

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L2224/13 ,  H01L2924/0002 ,  H05K1/0274 ,  H05K3/0014 ,  H05K3/0061 ,  H05K3/10 ,  H05K3/205 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/09409 ,  H05K2201/10106 ,  H05K2201/2054 ,  Y10T29/49155 ,  H01L2924/00

Abstract: There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating member on the heat sink; a wiring pattern embedded in the insulating member and including a first surface and a second surface opposite to the first surface, the second surface contacting the insulating member; and a metal layer on the first surface of the wiring pattern, wherein an exposed surface of the metal layer is flush with an exposed surface of the insulating member.

Abstract translation: 提供了布线基板。 布线基板包括：散热器; 散热器上的绝缘构件; 布线图案，其嵌入在所述绝缘构件中并且包括与所述第一表面相对的第一表面和第二表面，所述第二表面接触所述绝缘构件; 以及在所述布线图案的第一表面上的金属层，其中所述金属层的暴露表面与所述绝缘构件的暴露表面齐平。

公开(公告)号：US20150068032A1

公开(公告)日：2015-03-12

申请号：US14023757

申请日：2013-09-11

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H05K3/46

CPC classification number: G06F3/047 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04112 ,  H01L29/413 ,  H01L33/42 ,  H01L51/5215 ,  H05K1/0289 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/117 ,  H05K3/465 ,  H05K3/4664 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09845 ,  Y10T29/49155

Abstract: A method of making a multi-layer micro-wire structure includes providing a substrate having a substrate edge and first and second layers formed over the substrate. One or more micro-channels are imprinted in each of the first and second layers and first and second micro-wires located in the imprinted micro-channels, the micro-wires forming at least a portion of an exposed connection pad in each layer. The second layer edge is farther from the substrate edge than the first layer edge for at least a portion of the second layer edge so that the first connection pads are exposed through the second layer.

Abstract translation: 制造多层微线结构的方法包括提供具有衬底边缘的衬底和形成在衬底上的第一和第二层。 一个或多个微通道被印刷在第一和第二层中的每一个以及位于压印的微通道中的第一和第二微细线中，微线形成每个层中暴露的连接焊盘的至少一部分。 对于第二层边缘的至少一部分，第二层边缘比距第一层边缘更远离基板边缘，使得第一连接焊盘通过第二层曝光。

公开(公告)号：US20150061143A1

公开(公告)日：2015-03-05

申请号：US14318490

申请日：2014-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：US20150008589A1

公开(公告)日：2015-01-08

申请号：US14320836

申请日：2014-07-01

Applicant: Koei SUZUKI ,  Takanori TANO ,  Hiroshi MIURA ,  Atsushi ONODERA

Inventor： Koei SUZUKI ,  Takanori TANO ,  Hiroshi MIURA ,  Atsushi ONODERA

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/288 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76879 ,  H01L27/124 ,  H01L27/1292 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/1208 ,  H05K3/1258 ,  H05K3/4664 ,  H05K2201/0376 ,  H05K2203/107 ,  H05K2203/1173 ,  H01L2924/00

Abstract: A method of forming a stacked-layer wiring includes forming first wettability variable layer on a substrate using material that changes surface energy by energy application; forming first conductive layer in or on the first wettability variable layer; forming second wettability variable layer on the first wettability variable layer using material that changes surface energy by energy application; forming concave portion to become wiring pattern of second conductive layer to the second wettability variable layer while concurrently forming high surface energy area on surface exposed by forming the concave portion by changing surface energy; forming via hole by exposing a part of the first conductive layer while concurrently forming high surface energy area on surface exposed by forming the via hole by changing surface energy; and applying conductive ink to the high surface energy area to form the second conductive layer and via simultaneously.

Abstract translation: 形成堆叠层布线的方法包括：使用通过能量施加而改变表面能的材料在基板上形成第一润湿性变化层; 在第一润湿性变化层中或上面形成第一导电层; 使用通过能量施加改变表面能的材料在第一润湿性变化层上形成第二润湿性变化层; 形成凹部以成为第二导电层的布线图案到第二可润湿性变化层，同时通过改变表面能而形成凹部而露出的表面上形成高表面能区域; 通过暴露第一导电层的一部分而形成通孔，同时通过通过改变表面能形成通孔而在暴露的表面上形成高表面能区域; 以及将导电油墨施加到高表面能区域以形成第二导电层并同时通过。

公开(公告)号：US20140370705A1

公开(公告)日：2014-12-18

申请号：US14473266

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan ZHANG ,  Xiuyu CAI

IPC: H01L21/321 ,  H01L21/283

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

公开(公告)号：US08901728B2

公开(公告)日：2014-12-02

申请号：US14096504

申请日：2013-12-04

Applicant: Panasonic Corporation

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H01L23/48 ,  H01L23/04 ,  H05K1/11 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  G11B5/48 ,  H05K1/18 ,  H05K3/18 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.

Abstract translation: 提供了其中在表面上设置布线和焊盘部分的三维结构。 在三维结构的表面上设置用于布线的凹槽和用于焊盘部分的孔，其深度大于用于布线的凹槽的厚度。 用于焊盘部分的孔连续地设置有用于布线的凹槽。 布线导体的至少一部分嵌入到用于布线的凹槽中和用于垫部的孔中。

公开(公告)号：US08883020B2

公开(公告)日：2014-11-11

申请号：US13754170

申请日：2013-01-30

Applicant: Globalfoundries, Inc.

Inventor： Xunyuan Zhang ,  Xiuyu Cai

IPC: B44C1/22 ,  H05K3/00

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。

公开(公告)号：US08881381B2

公开(公告)日：2014-11-11

申请号：US12631594

申请日：2009-12-04

Applicant: Mi Sun Hwang ,  Myung Sam Kang ,  Ok Tae Kim ,  Seon Ha Kang ,  Gil Yong Shin ,  Kil Yong Yun ,  Min Jung Cho

Inventor： Mi Sun Hwang ,  Myung Sam Kang ,  Ok Tae Kim ,  Seon Ha Kang ,  Gil Yong Shin ,  Kil Yong Yun ,  Min Jung Cho

IPC: H05K3/36 ,  H05K3/10 ,  H05K3/20 ,  H05K3/46 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K3/4685 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.

Abstract translation: 本文公开了一种制造印刷电路板的方法，包括：制备第一载体，其包括在其一侧上形成的第一图案; 制备包括在其一侧上顺序形成的第一阻焊层和第二图案的第二载体; 按压第一载体和第二载体，使得第一图案嵌入绝缘层的一侧，并且将第二图案嵌入绝缘层的另一侧，然后移除第一载体和第二载体以制造两个基板 ; 使用粘合层将两个基板彼此连接，使得第一阻焊层彼此面对; 以及形成用于在绝缘层中连接第一图案与第二图案的通孔，在设置有第一图案的绝缘层上形成第二阻焊剂，然后除去粘合层。

公开(公告)号：US20140209358A1

公开(公告)日：2014-07-31

申请号：US13751450

申请日：2013-01-28

Applicant: JOHN ANDREW LEBENS ,  David Paul Trauernicht ,  Yongcai Wang ,  Ronald Steven Cok

Inventor： JOHN ANDREW LEBENS ,  David Paul Trauernicht ,  Yongcai Wang ,  Ronald Steven Cok

IPC: H05K1/02

CPC classification number: H05K1/0296 ,  G06F3/044 ,  H05K1/02 ,  H05K1/0289 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09681 ,  H05K2201/09727 ,  Y10T428/26

Abstract: An electrical conductor includes a substrate having micro-channels formed in the substrate. A plurality of spaced-apart first micro-wires is located on or in the micro-channels, the first micro-wires extending across the substrate in a first direction. A plurality of spaced-apart second micro-wires is located on or in the micro-channels, the second micro-wires extending across the substrate in a second direction different from the first direction. Each second micro-wire is electrically connected to at least two first micro-wires and at least one of the second micro-wires has a width less than the width of at least one of the first micro-wires.

Abstract translation: 电导体包括在衬底中形成有微通道的衬底。 多个间隔开的第一微电线位于微通道上或微通道中，第一微电线在第一方向上延伸穿过衬底。 多个间隔开的第二微电线位于微通道上或微通道中，第二微电线沿与第一方向不同的第二方向延伸穿过衬底。 每个第二微线电连接到至少两个第一微线，并且至少一个第二微线的宽度小于第一微线中的至少一个的宽度。