公开(公告)号：US10176006B2

公开(公告)日：2019-01-08

申请号：US15212360

申请日：2016-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lisa Cranton Heller

IPC: G06F9/455 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/109

Abstract: Virtual machine purging of structures associated with address translation is delayed. A host logical processor executing on a physical processor issues a local purge request to purge entries of a structure associated with address translation. The structure associated with address translation includes one or more host entries for the host logical processor and one or more guest entries for a guest virtual processor running on the physical processor. Based on issuing the local purge request, an indicator is set to control purging of the one or more guest entries of the structure associated with address translation. Further, purging of the one or more guest entries of the guest virtual processor is delayed for consideration of purging at dispatch of the guest virtual processor.

公开(公告)号：US20180357178A1

公开(公告)日：2018-12-13

申请号：US15620017

申请日：2017-06-12

Applicant: ARM LIMITED

Inventor： Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA ,  Matthew Lucien EVANS ,  Paul Gilbert MEYER ,  Andrew Brookfield SWAINE

IPC: G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

CPC classification number: G06F12/1036 ,  G06F12/0802 ,  G06F12/1425 ,  G06F13/1668

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

公开(公告)号：US10152602B2

公开(公告)日：2018-12-11

申请号：US14748883

申请日：2015-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： David Kaplan ,  Leendert van Doorn ,  Joshua Schiffman

IPC: G06F9/455 ,  G06F21/60 ,  G06F12/14 ,  G06F12/1036 ,  G06F21/53

Abstract: A processing system includes a processor that implements registers to define a state of a virtual machine (VM) running on the processor. The processor detects exit conditions of the VM. The processing system also includes a memory element to store contents of the registers in a first data structure that is isolated from a hypervisor of the VM in response to the processor detecting an exit condition. The VM is to selectively expose contents of a subset of the registers to the hypervisor.

公开(公告)号：US10146699B2

公开(公告)日：2018-12-04

申请号：US15500576

申请日：2015-04-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mark David Lillibridge ,  Paolo Faraboschi

IPC: G06F12/02 ,  G06F12/1036 ,  G06F12/0804

Abstract: Apertures of a first size in a first physical address space of at least one processor are mapped to respective blocks of the first size in a second address space of a storage medium. Apertures of a second size in the first physical address space are mapped to respective blocks of the second size in the second address space, the second size being different from the first size.

公开(公告)号：US10083131B2

公开(公告)日：2018-09-25

申请号：US14566945

申请日：2014-12-11

Applicant: Ampere Computing LLC

Inventor： Tanmay Sunit Inamdar ,  Ravi Rajendra Patel

IPC: G06F12/14 ,  G06F12/1036 ,  H04L12/861

CPC classification number: G06F12/1475 ,  G06F12/1036 ,  G06F12/14 ,  G06F2212/1052 ,  G06F2212/657 ,  H04L49/90 ,  H04L49/901

Abstract: Various aspects facilitate implementing a memory translation table associated with key-based indexing. A table component is configured for generating a memory translation table and a key component is configured for allocating a key associated with a memory access based on a virtual address and a set of access permissions. A descriptor component is configured for generating a descriptor associated with the memory translation table that comprises at least the set of access permissions and a portion of the key.

公开(公告)号：US20180232141A1

公开(公告)日：2018-08-16

申请号：US15430347

申请日：2017-02-10

Applicant: International Business Machines Corporation

Inventor： Amalia Avraham ,  Shay Berman ,  Ran Harel ,  Rivka M. Matosevich

IPC: G06F3/06 ,  G06F12/1036

Abstract: A computer-implemented method according to one embodiment includes identifying a host within a container environment, and mapping a volume of a container to the host within the container environment, utilizing small computer system interface (SCSI) second level addressing.

公开(公告)号：US10042778B2

公开(公告)日：2018-08-07

申请号：US15475718

申请日：2017-03-31

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F13/12 ,  G06F12/1036 ,  G06F12/1009 ,  G06F9/50

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

公开(公告)号：US20180210842A1

公开(公告)日：2018-07-26

申请号：US15416549

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/657 ,  G06F2212/683 ,  G06F2212/684

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

公开(公告)号：US10007619B2

公开(公告)日：2018-06-26

申请号：US14859351

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Carlos Javier Moreira ,  Alexander Miretsky ,  Meghal Varia ,  Kyle John Ernewein ,  Manokanthan Somasundaram ,  Muhammad Umar Choudry ,  Serag Monier Gadelrab

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/1045 ,  G06F12/0891 ,  G06F12/0844 ,  G06F12/1036 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/50 ,  G06F2212/655 ,  G06F2212/682 ,  G06F2212/683 ,  G06F2212/684

Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

公开(公告)号：US20180165133A1

公开(公告)日：2018-06-14

申请号：US15638894

申请日：2017-06-30

Applicant: Microsoft Technology Licensing, LLC

Inventor： Mehmet Iyigun ,  Matthew David Kurjanowicz ,  Martijn de Kort ,  Kevin M. Broas ,  Yevgeniy M. Bak

IPC: G06F9/50 ,  G06F9/455 ,  G06F12/1036 ,  G06F9/48 ,  H04L29/08 ,  G06F12/14

Abstract: A computing device runs a host on which multiple guests (e.g., virtual machines run via a virtual machine monitor such as a hypervisor) can run. The guest is used for isolation as well as hardware resource partitioning. The guest and the host agree on a name and a size for shared memory. Both the guest and the host map to the shared memory, and both the guest and the host to access the shared memory. The access allowed to the shared memory can be the same for both the host and the guest (e.g., both may be allowed read/write access) or different (e.g., the guest may be allowed write only access and the host may be allowed read only access).