公开(公告)号：US06745293B2

公开(公告)日：2004-06-01

申请号：US09932308

申请日：2001-08-17

Applicant: Serge Lasserre ,  Gerard Chauvel

Inventor： Serge Lasserre ,  Gerard Chauvel

IPC: G06F1200

CPC classification number: G06F9/5011 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0879 ,  G06F12/0891 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2209/5021 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry.

Abstract translation: 数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。 共享的L2高速缓存体系结构体现为4路关联性，每个条目有4个段和4个有效位和脏位。 多个检测电路同时响应多个缓存访问请求。 如果并发命中由检测电路确定，高速缓存服务中的多个端口将同时发送多个请求者。

公开(公告)号：US06738864B2

公开(公告)日：2004-05-18

申请号：US09932359

申请日：2001-08-17

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F1208

CPC classification number: G06F12/084 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F12/0842 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2212/1028 ,  G06F2212/681 ,  Y02D10/13 ,  Y02D10/24

Abstract: A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays (502(n)), four segments per entry and four valid and dirty bits. Each tag entry (1236) includes task-ID qualifier field (522) and a resource ID qualifier field (520). Accesses to the cache are qualified by comparing (1244) a task ID and resource ID proffered with a cache request to values stored in the tag entry.

Abstract translation: 数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。 共享的L2高速缓存架构体现为与相应的标签阵列（502（n）），每个条目四个段和四个有效位和脏位的四路关联性。 每个标签条目（1236）包括任务ID限定符字段（522）和资源ID限定字段（520）。 通过将任务ID和提供缓存请求的资源ID与存储在标签条目中的值进行比较（1244）来限制访问高速缓存。

公开(公告)号：US06728837B2

公开(公告)日：2004-04-27

申请号：US09985426

申请日：2001-11-02

Applicant: John Wilkes ,  Theodore M. Wong

Inventor： John Wilkes ,  Theodore M. Wong

IPC: G06F1200

CPC classification number: G06F12/122 ,  G06F11/3409 ,  G06F12/0866 ,  G06F12/0888 ,  G06F12/123 ,  G06F2201/885

Abstract: A computer system cache monitors the effectiveness of data inserted into a cache by one or more sources to determine which source should receive preferential treatment when updating the cache. The cache may be part of a computer system that includes a plurality of host systems, each host system includes a host cache, connected to a storage system having a storage system cache. Ghost caches are used to record hits from the plurality of host systems performing operations for storing and retrieving data from the storage system cache. The storage system cache includes a cache controller that is operable to calculate a merit figure and determine an insertion point in a queue associated with the storage system cache based on the merit figure. The merit figure is calculated using a weighting algorithm for weighting hits from the plurality of sources recorded in the ghost caches.

Abstract translation: 计算机系统高速缓存监视由一个或多个源插入到高速缓存中的数据的有效性，以确定在更新高速缓存时哪些源应该接收优先处理。 高速缓存可以是包括多个主机系统的计算机系统的一部分，每个主机系统包括连接到具有存储系统高速缓存的存储系统的主机高速缓存。 Ghost高速缓存用于记录来自多个主机系统的命中，执行用于从存储系统高速缓存存储和检索数据的操作。 存储系统高速缓存包括高速缓存控制器，该高速缓存控制器可操作以基于优点图来计算优点图并确定与存储系统高速缓存相关联的队列中的插入点。 使用加权算法计算优点数字，用于对记录在虚拟高速缓存中的多个源加权命中。

公开(公告)号：US06622189B2

公开(公告)日：2003-09-16

申请号：US09726274

申请日：2000-11-30

Applicant: Raymond Morris Bryant ,  William Henry Hartner

Inventor： Raymond Morris Bryant ,  William Henry Hartner

IPC: G06F946

CPC classification number: G06F9/52 ,  G06F11/3466 ,  G06F12/0806 ,  G06F2201/825 ,  G06F2201/885

Abstract: A method and apparatus is presented for controlling spin lock instrumentation for a spin lock in a system with a cache. A lock flag represents a busy state for the spin lock; a first instrumentation flag is a global variable representing an enablement state for the spin lock instrumentation. A second instrumentation flag, stored within the same cache line as the lock flag, is also maintained as an updateable indication of the first instrumentation flag. Prior to each acquirement of the spin lock, the second instrumentation flag is checked for an indication that spin lock instrumentation is enabled. Although a reading of the lock flag may generate a cache miss, the lock flag is necessarily checked upon attempting to acquire the lock; the check of the second instrumentation flag cannot generate a superfluous cache miss because the second instrumentation flag is in the same cache line as the lock flag.

Abstract translation: 提出了一种用于控制具有高速缓存的系统中的自旋锁的自旋锁定装置的方法和装置。 锁定标志表示自旋锁的忙状态; 第一个仪器标志是表示旋转锁定仪表的启用状态的全局变量。 存储在与锁定标志相同的高速缓存行中的第二仪器标志也被保持为第一仪器标志的可更新指示。 在每次获得自旋锁之前，检查第二个仪器标志是否启用自动锁定仪器的指示。 虽然锁定标志的读取可能产生高速缓存未命中，但是在尝试获取锁定时必须检查锁定标志; 第二个仪器标志的检查不能产生多余的高速缓存未命中，因为第二个仪器标志位于与锁定标志相同的高速缓存行中。

公开(公告)号：US06611926B1

公开(公告)日：2003-08-26

申请号：US09450826

申请日：1999-11-29

Applicant: Blaine D. Gaither ,  Donna Ott

Inventor： Blaine D. Gaither ,  Donna Ott

IPC: H02H305

CPC classification number: G06F11/349 ,  G06F11/3485 ,  G06F12/0831 ,  G06F2201/885

Abstract: A device and method for collecting data on which lines are being shared in a multiprocessor system having cache memories is described. In the present invention, a sample arm register observes a local channel, such as a bus, for key events. Upon waiting a certain number of events, the sample arm register arms a sample register. Once armed the sample register will latch the next qualified address of the data being collected. The sampled data is then stored in memory. Post processing software will read the data from memory. The samples are then analyzed to correlate them with such things as locations and data structures in the system. This helps dynamically optimize the work load to reduce shared dirty line traffic.

Abstract translation: 描述用于收集在具有高速缓冲存储器的多处理器系统中共享线路的数据的装置和方法。 在本发明中，样本臂寄存器观察诸如总线的本地信道用于关键事件。 在等待一定数量的事件时，采样臂寄存器装载一个采样寄存器。 一旦布防，样品寄存器将锁定正在收集的数据的下一个合格地址。 然后将采样数据存储在存储器中。 后处理软件将从内存读取数据。 然后分析样本以将它们与系统中的位置和数据结构等相关联。 这有助于动态优化工作负载，以减少共享脏线流量。

公开(公告)号：US20030088739A1

公开(公告)日：2003-05-08

申请号：US09985426

申请日：2001-11-02

Inventor： John Wilkes ,  Theodore M. Wong

IPC: G06F012/00

CPC classification number: G06F12/122 ,  G06F11/3409 ,  G06F12/0866 ,  G06F12/0888 ,  G06F12/123 ,  G06F2201/885

Abstract: A computer system cache monitors the effectiveness of data inserted into a cache by one or more sources to determine which source should receive preferential treatment when updating the cache. The cache may be part of a computer system that includes a plurality of host systems, each host system includes a host cache, connected to a storage system having a storage system cache. Ghost caches are used to record hits from the plurality of host systems performing operations for storing and retrieving data from the storage system cache. The storage system cache includes a cache controller that is operable to calculate a merit figure and determine an insertion point in a queue associated with the storage system cache based on the merit figure. The merit figure is calculated using a weighting algorithm for weighting hits from the plurality of sources recorded in the ghost caches.

Abstract translation: 计算机系统高速缓存监视由一个或多个源插入到高速缓存中的数据的有效性，以确定在更新高速缓存时哪个源应该接收优先处理。 高速缓存可以是包括多个主机系统的计算机系统的一部分，每个主机系统包括连接到具有存储系统高速缓存的存储系统的主机高速缓存。 Ghost高速缓存用于记录来自多个主机系统的命中，执行用于从存储系统高速缓存存储和检索数据的操作。 存储系统高速缓存包括高速缓存控制器，该高速缓存控制器可操作以基于优点图来计算优点图并确定与存储系统高速缓存相关联的队列中的插入点。 使用加权算法计算优点数字，用于对记录在虚拟高速缓存中的多个源加权命中。

公开(公告)号：US20030088738A1

公开(公告)日：2003-05-08

申请号：US10003857

申请日：2001-11-02

Inventor： David B. Fox ,  Joseph M. Hoke ,  Tin-Chee Lo

IPC: G06F012/00

CPC classification number: G06F11/3636 ,  G06F11/348 ,  G06F12/0802 ,  G06F2201/885 ,  G06F2212/2515

Abstract: A method is disclosed for instructing a computing system to allocate a trace array from an original cache memory, where the method includes dividing the original cache memory into a reduced-size cache memory and a trace array, permitting storage of trace signal data into the trace array, and permitting retrieval of the trace signal data from the trace array.

Abstract translation: 公开了一种用于指示计算系统从原始高速缓冲存储器分配跟踪阵列的方法，其中该方法包括将原始高速缓存存储器分为缩小大小的高速缓冲存储器和跟踪阵列，允许将跟踪信号数据存储到跟踪中 阵列，并允许从跟踪数组中检索跟踪信号数据。

公开(公告)号：US06542855B1

公开(公告)日：2003-04-01

申请号：US09309137

申请日：1999-05-10

Applicant: Timothy A. Pontius

Inventor： Timothy A. Pontius

IPC: G06F1500

CPC classification number: G06F11/3457 ,  G06F12/0802 ,  G06F2201/885

Abstract: A method of selecting a cache design for a computer system begins with the making of a prototype module with a processor, a “seed” cache, and a trace detection module. The prototype module can be inserted within a system that includes main memory and peripherals. While an application program is run on the system, the communications between the processor and the seed cache are detected and compressed. The compressed detections are stored in a trace capture module and collectively define a trace of the program on the prototype module. The trace is then expanded and used to evaluate a candidate cache design. The expansion and evaluation can be iterated to evaluate many cache designs. The method can be used to pick the cache design with the best performance or as a foundation for performing a cost/performance comparison of the evaluated caches. In this method, a single prototype is used to generate an accurate trace that permits many alternative cache designs to be evaluated. This contrasts with methods that use cacheless models to develop less accurate traces and methods that allow only one cache design to be evaluated per prototype. In summary, the invention provides an accurate and efficient method of evaluating alternative cache designs.

Abstract translation: 选择用于计算机系统的高速缓存设计的方法开始于具有处理器，“种子”高速缓存和跟踪检测模块的原型模块的制造。 原型模块可以插入包含主存储器和外围设备的系统中。 当应用程序在系统上运行时，处理器和种子高速缓存之间的通信被检测和压缩。 压缩的检测存储在跟踪捕获模块中，并共同定义原型模块上程序的跟踪。 然后，跟踪被扩展并用于评估候选缓存设计。 可以迭代扩展和评估来评估许多缓存设计。 该方法可用于选择具有最佳性能的缓存设计或作为执行评估的缓存的成本/性能比较的基础。 在该方法中，使用单个原型来生成允许评估许多备用高速缓存设计的精确跟踪。 这与使用无高速缓存模型开发不太准确的跟踪和方法的方法形成对比，只允许每个原型对一个缓存设计进行评估。 总之，本发明提供了一种评估替代缓存设计的准确和有效的方法。

公开(公告)号：US20030051191A1

公开(公告)日：2003-03-13

申请号：US09948757

申请日：2001-09-10

Inventor： Edgar Circenis ,  Brad Klein

IPC: G06F011/26

CPC classification number: G06F11/3409 ,  G06F11/3466 ,  G06F2201/885

Abstract: A problem detection system detects problems related with operation of a computer system, its hardware components, application programs, and databases. The problem detection system begins by gathering or discovering initial data from one or more of the hardware components, application programs, and databases. The problem detection system may then update this data over time. The problem detection system includes mechanism for discovering problems in the computer system. The problem detection system also includes mechanisms for reporting problems to a user of the computer system or to a system administrator. The problem detection system may report the problems to other components of the computer system, may store data related to the problems, and may present the problem information to the user through a separate display

Abstract translation: 问题检测系统检测与计算机系统，其硬件组件，应用程序和数据库的操作有关的问题。 问题检测系统首先从一个或多个硬件组件，应用程序和数据库收集或发现初始数据。 问题检测系统随后可以更新该数据。 问题检测系统包括用于发现计算机系统中的问题的机制。 问题检测系统还包括用于向计算机系统的用户或系统管理员报告问题的机制。 问题检测系统可以将问题报告给计算机系统的其他组件，可以存储与问题相关的数据，并且可以通过单独的显示向用户呈现问题信息

公开(公告)号：US06530042B1

公开(公告)日：2003-03-04

申请号：US09436108

申请日：1999-11-08

Applicant: Joel Roger Davidson ,  Judith E. K. Laurens ,  Alexander Erik Mericas

Inventor： Joel Roger Davidson ,  Judith E. K. Laurens ,  Alexander Erik Mericas

IPC: G06F1130

CPC classification number: G06F11/3409 ,  G06F11/3452 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A method and apparatus for monitoring an internal queue within a processor, such as an instruction completion table or instruction re-order buffer, is presented. The performance monitoring unit of the processor contains multiple counters, and each counter counts occurrences of specified events. An internal queue of the processor may be specified to be monitored. A count of event signals indicating a successful allocation request for an entry in the internal queue is divided by a count of event signals indicating a passage of units of time to obtain the average rate for allocation requests for queue entries in the specified internal queue. A count of event signals indicating an occupation of a specific entry in the internal queue during a unit of time is divided by a count of event signals indicating an allocation of a specific entry in the internal queue to obtain the average time spent in the internal queue. An average number of entries in the internal queue is computed as a product of the average rate for allocation requests for queue entries and the average time spent in the internal queue. An event signal that indicates failure of an allocation request for an entry in the internal queue may be monitored.

Abstract translation: 提出了一种用于监视处理器内的内部队列的方法和装置，例如指令完成表或指令重新排序缓冲器。 处理器的性能监视单元包含多个计数器，每个计数器计数指定事件的出现次数。 可以指定处理器的内部队列进行监视。 指示对内部队列中的条目的成功分配请求的事件信号的计数除以指示通过时间单位的事件信号的计数，以获得指定的内部队列中的队列条目的分配请求的平均速率。 指示在时间单位内对内部队列中的特定条目的占用的事件信号的计数除以表示内部队列中的特定条目的分配的事件信号的计数，以获得在内部队列中花费的平均时间 。 内部队列中的平均条目数量计算为队列条目的分配请求的平均速率和在内部队列中花费的平均时间的乘积。 可以监视指示内部队列中的条目的分配请求失败的事件信号。