公开(公告)号：US20060110838A1

公开(公告)日：2006-05-25

申请号：US11324220

申请日：2006-01-04

Applicant: Akio Rokugawa ,  Takahiro Iijima

Inventor： Akio Rokugawa ,  Takahiro Iijima

IPC: H01L21/66

CPC classification number: H01L23/49531 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/48 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K1/113 ,  H05K3/0061 ,  H05K3/205 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/09527 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A multi-layered circuit substrate for a semiconductor device comprises a multi-layered circuit substrate body having first and second surfaces and comprising a plurality of conductive pattern layers integrally laminated one on the other from the first surface to the second surface, so that a plurality of semiconductor device elements can be arranged on the first surface of the substrate body; and a plate member, a rigidity thereof being higher than that of the substrate body, attached to the second surface of the substrate body. A plurality of semiconductor elements can be mounted on the semiconductor element mounting surface defined on the first surface of the substrate body.

公开(公告)号：US20050017271A1

公开(公告)日：2005-01-27

申请号：US10920270

申请日：2004-08-18

Applicant: Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/38 ,  H05K3/46 ,  H01L23/52

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A substrate of multilayered structure having a. plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract translation: 具有a的多层结构的衬底。 多个绝缘层和布线层组，并且具有用于安装半导体元件的一个面和要设置外部连接端子的另一个面，用于安装半导体元件的面设置有衬垫 接合到半导体元件的电极端子，另一个面设置有待连接到诸如由焊球形成的端子的外部连接端子的焊盘，并且绝缘层两侧的布线层被连接 彼此通过穿过绝缘层的通孔，其中要结合到半导体元件的电极端子的焊盘的表面是平坦的并且在同一平面中。 还公开了制造这种多层基板的方法。

公开(公告)号：US20020117331A1

公开(公告)日：2002-08-29

申请号：US10006547

申请日：2001-12-04

Applicant: Japan Radio Co., Ltd.

Inventor： Shigetoshi Abe ,  Tomoko Kato ,  Yasuo Sato ,  Takashi Itagaki ,  Kenji Matsumoto

IPC: H05K001/11

CPC classification number: H05K3/421 ,  H05K1/113 ,  H05K3/064 ,  H05K3/386 ,  H05K3/427 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/063 ,  H05K2203/1394 ,  Y10T29/49156 ,  Y10T29/49213 ,  Y10T29/49218

Abstract: A method includes the steps of forming a first metal foil (82) on a surface of an insulator substrate (1a), drilling, with a thermosetting resin film (84) temporarily fixed to an opposite surface of the substrate, a through hole (86) simultaneously in the first foil, the substrate, and the resin film, simultaneously heating and vacuum-pressing the first foil, the substrate, the resin film, and a second metal foil (87) brought into contact with the resin film to obtain an intermediate board in which a bottom of the through hole is covered with the second foil and has a corner with a corner rounded portion (93) formed by the resin film, and forming a metal plating layer (95) on the first and the second foils, on the bottom and an inner wall of the through hole, and on the corner rounded portion to obtain a final printed wiring board.

Abstract translation: 一种方法包括以下步骤：在绝缘体基板（1a）的表面上形成第一金属箔（82），用临时固定到基板的相对表面的热固性树脂膜（84）进行钻孔;通孔（86） ）同时对第一箔，基板和树脂膜同时进行加热和真空压制第一箔，基板，树脂膜和与树脂膜接触的第二金属箔（87），以获得 中间板，其中通孔的底部被第二箔覆盖，并且具有由树脂膜形成的角圆角部分（93）的拐角，并且在第一和第二箔上形成金属镀层（95） ，在通孔的底部和内壁上，并且在角落圆形部分上，以获得最终的印刷线路板。

公开(公告)号：US06441314B2

公开(公告)日：2002-08-27

申请号：US09815047

申请日：2001-03-23

Applicant: Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H05K116

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

公开(公告)号：US6143117A

公开(公告)日：2000-11-07

申请号：US460484

申请日：1999-12-14

Applicant: Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

Inventor： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B43/00 ,  B44C1/165 ,  H01L21/68 ,  H05K3/00 ,  H05K3/02 ,  H05K3/28 ,  H05K3/46

CPC classification number: B32B43/00 ,  H01L21/6835 ,  H05K3/025 ,  H05K3/4614 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  H05K3/007 ,  H05K3/28 ,  H05K3/4623 ,  H05K3/467 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Abstract translation: 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

公开(公告)号：US6036809A

公开(公告)日：2000-03-14

申请号：US250882

申请日：1999-02-16

Applicant: Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

Inventor： Kimberley A. Kelly ,  Ashwani K. Malhotra ,  Eric D. Perfecto ,  Roy Yu

IPC: B32B43/00 ,  B44C1/165 ,  H01L21/68 ,  H05K3/00 ,  H05K3/02 ,  H05K3/28 ,  H05K3/46 ,  B32B31/00 ,  H01B13/00 ,  H01L29/12 ,  B32B4/00

CPC classification number: B32B43/00 ,  H01L21/6835 ,  H05K3/025 ,  H05K3/4614 ,  B32B2310/0843 ,  B32B2311/00 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/3025 ,  H05K2201/09527 ,  H05K2201/10666 ,  H05K2203/016 ,  H05K2203/107 ,  H05K3/007 ,  H05K3/28 ,  H05K3/4623 ,  H05K3/467 ,  Y10S156/922 ,  Y10S438/94 ,  Y10S438/974 ,  Y10S438/977 ,  Y10T156/11 ,  Y10T156/1158 ,  Y10T428/12528 ,  Y10T428/12583

Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing. The process of the present invention has at least three, specific applications: (1) the thin-film structure and metal interconnect can be released to yield a free-standing film; (2) the thin-film structure and metal interconnect can be laminated onto a permanent substrate (when building top-side down structures) and then released; and (3) the thin-film structure can be transferred to a secondary temporary carrier (when building top-side up structures) for further processing and testing, then transferred to a permanent substrate before releasing the thin-film structure and metal interconnect.

Abstract translation: 用于从主载体制造和释放薄膜结构以进一步处理的工艺。 薄膜结构建立在设置在电介质层上的金属互连上，其又沉积在主载体上。 薄膜结构和金属互连通过限定在金属互连和电介质膜之间的释放界面从电介质层和初级载体释放。 通过激光烧蚀或切割来干扰界面来实现释放。 本发明的方法具有至少三个具体应用：（1）可以释放薄膜结构和金属互连以产生独立的膜; （2）薄膜结构和金属互连可以层压在永久性基板上（当构建顶部向下结构时）然后释放; （3）可以将薄膜结构转移到二次临时载体（当构建顶侧上部结构）进行进一步的加工和测试时，在释放薄膜结构和金属互连之前转移到永久基板。

公开(公告)号：US5774340A

公开(公告)日：1998-06-30

申请号：US697655

申请日：1996-08-28

Applicant: Chi Shih Chang ,  Frank Daniel Egitto

Inventor： Chi Shih Chang ,  Frank Daniel Egitto

IPC: H01L23/50 ,  H01L23/538 ,  H05K1/11 ,  H05K3/46 ,  H01R9/09

CPC classification number: H05K3/462 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H05K1/113 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A self-supporting redistribution structure for directly mounting a semi-conductor chip to a multilayer electronic substrate is separately fabricated and then laminated to the multilayer substrate. The redistribution structure comprises a dielectric layer having plated vias communicating between its two major surfaces, redistribution lines and input/output pads on its upper major surface and joining patterns on its lower margin surface for electrical connection with the multilayer substrate. The metal plating in the plated vias of the redistribution device connects respective input/output pads on the upper surface of the redistribution structures with the joining patterns on its lower major surface. Input/output pads define an even (planar) topography with the redistribution lines to facilitate flip chip joining.

Abstract translation: 分别制造用于将半导体芯片直接安装到多层电子基板的自支撑再分布结构，然后层叠到多层基板。 再分布结构包括具有在其两个主表面之间连通的电镀通孔的电介质层，再分配线和其上主表面上的输入/输出焊盘，并且在其下边缘表面上连接图案以与多层基板电连接。 再分配装置的电镀通孔中的金属电镀将再分布结构的上表面上的相应输入/输出焊盘与其下主表面上的接合图案相连。 输入/输出焊盘用再分布线限定均匀（平面）形貌，以便于倒装芯片连接。

公开(公告)号：US5495665A

公开(公告)日：1996-03-05

申请号：US336107

申请日：1994-11-04

Applicant: Richard W. Carpenter ,  Robert E. Ruane

Inventor： Richard W. Carpenter ,  Robert E. Ruane

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

CPC classification number: H05K3/421 ,  H05K1/113 ,  H05K3/0097 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/0156 ,  H05K2203/1536 ,  H05K3/20 ,  H05K3/427 ,  Y10T29/49126

Abstract: A process for connecting at least two electrically conductive patterns through a dielectric material by a landless electrical connection is provided. The process includes providing a composite containing a dielectric substrate having a conductive plane on at least one of its major surfaces and a temporary support layer covering the conductive plane. Blind vias are provided in the dielectric substrate and are plated with an electrically conductive material. The temporary support layer is removed thereby providing a landless electrical connection through the dielectric material and the conductive plane is available for providing external electrical conductive pattern.

Abstract translation: 提供了一种通过无轨电连接通过电介质材料连接至少两个导电图案的工艺。 该方法包括提供一种复合材料，该复合材料包含在其主要表面中的至少一个上具有导电平面的电介质基底和覆盖该导电平面的临时支撑层。 盲孔设置在电介质基片中并镀有导电材料。 移除临时支撑层，从而提供通过介电材料的无地电连接，并且导电平面可用于提供外部导电图案。

公开(公告)号：US09980383B2

公开(公告)日：2018-05-22

申请号：US14748623

申请日：2015-06-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki Yosui ,  Masahiro Ozawa

IPC: H01H47/00 ,  H05K1/16 ,  H01L23/498 ,  H01G4/40 ,  H01G2/06 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H01F17/00 ,  H05K3/38

CPC classification number: H05K1/162 ,  H01F17/0006 ,  H01G2/06 ,  H01G4/40 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K1/165 ,  H05K3/383 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2203/0278 ,  H05K2203/0307

Abstract: Sheets are laminated on each other and pressure bonded with fixtures from upper and lower directions of a lamination direction while being heated to produce a laminated circuit substrate including therein a capacitor and a coil. The capacitor is defined by a first conductor pattern and a second conductor pattern that face each other across thermoplastic resin layers. In the laminated circuit substrate, the first conductor pattern includes a first principal surface, the second conductor pattern includes a second principal surface, the first principal surface faces the second conductor pattern, the second principal surface faces the first conductor pattern, and the first principal surface and the second principal surface are subject to a roughening process.

公开(公告)号：US09949372B2

公开(公告)日：2018-04-17

申请号：US15441540

申请日：2017-02-24

Applicant: IBIDEN CO., LTD.

Inventor： Teruyuki Ishihara ,  Hiroyuki Ban ,  Haiying Mei

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/20 ,  H05K3/28 ,  H05K3/30 ,  H05K3/38 ,  H05K3/40 ,  H01L23/495 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L23/49534 ,  H01L2224/16225 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/113 ,  H05K3/0061 ,  H05K3/025 ,  H05K3/205 ,  H05K3/243 ,  H05K3/284 ,  H05K3/303 ,  H05K3/388 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09527 ,  H05K2201/10674 ,  H01L2924/00012

Abstract: A printed wiring board includes a laminate, a wiring layer formed on first main surface of the laminate and including conductor pads, via conductors including first and second via conductors and formed in the laminate such that each via conductor has diameter gradually reducing from the first main surface toward second main surface of the laminate, and conductor post formed on the first via conductors such that each conductor post includes a metal foil and a plating layer formed on the metal foil. The via conductors are formed such that the first via conductors are positioned in an outer edge portion of the laminate and have minimum-diameter-side surfaces positioned to form a same plane with the second main surface of the laminate and that the second via conductors are positioned in a central portion of the laminate and have minimum-diameter-side surfaces recessed from the second main surface of the laminate.