公开(公告)号：US20140084460A1

公开(公告)日：2014-03-27

申请号：US14094714

申请日：2013-12-02

Applicant: SMARTRAC TECHNOLOGY GmbH

Inventor： Carsten Nieland ,  Frank Kriebel

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H05K1/18 ,  G06K19/077 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13599 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81206 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/8149 ,  H01L2224/81898 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/00014 ,  H05K3/301 ,  H05K3/325 ,  H05K2201/1059 ,  H05K2201/10674 ,  H05K2201/10954 ,  H05K2203/0278 ,  H05K2203/041 ,  Y10T29/49018 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05552 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/03

Abstract: Contact bumps between a contact pad and a substrate can include recesses and protrusions that can mate with the material of the substrate. The irregular mating surfaces between the contact bumps and the contact pads can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart cards.

Abstract translation: 接触焊盘和基板之间的接触凸块可以包括可与基板的材料配合的凹部和凸起。 接触凸块和接触垫之间的不规则配合表面可以增强接触件的接合强度，例如抗剪切力和张力，特别是对于柔性系统如智能卡。

公开(公告)号：US08683413B2

公开(公告)日：2014-03-25

申请号：US13621242

申请日：2012-09-15

Applicant: Wiren Dale Becker ,  Jinwoo Choi ,  Tingdong Zhou

Inventor： Wiren Dale Becker ,  Jinwoo Choi ,  Tingdong Zhou

IPC: G06F17/50 ,  G06F9/455 ,  H01L21/00

CPC classification number: H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K3/4629 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Abstract translation: 多层陶瓷封装包括：具有需要供电的识别芯片/器件区域的信号层; 以及设置在信号层正上方或下方并相邻的相对侧上的电压功率（Vdd）层和接地（Gnd）层，并提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。 混合网格方案包括：在识别的芯片/设备区域的正上方或下方的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 和所有其他区域中的较宽的网格间距Vdd迹线对齐以与其他区域的信号线平行并相邻。 在与信号线平行且相邻的网格区域内提供更宽的轨迹。

公开(公告)号：US08671565B1

公开(公告)日：2014-03-18

申请号：US12800757

申请日：2010-05-21

Applicant: Bob Shih-Wei Kuo

Inventor： Bob Shih-Wei Kuo

IPC: H01R43/00 ,  H05K13/00

CPC classification number: H05K1/116 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/045 ,  H05K3/107 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/2072 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49176 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture pad, a focused laser beam is moved linearly to form linear channels in the dielectric layer. These channels are filled with an electrically conductive material to form the capture pad.

Abstract translation: 捕获垫结构包括下介电层，嵌入在下介电层内的捕获垫，捕获垫包括多个线性段。 为了形成捕获垫，聚焦的激光束线性地移动以在介电层中形成线性通道。 这些通道填充有导电材料以形成捕获垫。

公开(公告)号：US20140061882A1

公开(公告)日：2014-03-06

申请号：US14077126

申请日：2013-11-11

Applicant: SK hynix Inc.

Inventor： Peter C. Salmon

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

Abstract: A circuit assembly includes a plurality of integrated circuits having stud bumps at each input/output pad, an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said stud bumps of said integrated circuits, and electrical and mechanical bonding at each of said input/output pads, wherein each of said stud bumps connects with solder in each of said wells to form a permanent connection.

Abstract translation: 电路组件包括多个集成电路，每个集成电路在每个输入/输出焊盘处具有柱形突起，互连电路具有填充有焊料的阱，所述阱与所述集成电路的所述柱形突起以一对一关系对应， 以及在每个所述输入/输出焊盘处的机械接合，其中每个所述柱形凸块与每个所述孔中的焊料连接以形成永久连接。

公开(公告)号：US08654538B2

公开(公告)日：2014-02-18

申请号：US13050217

申请日：2011-03-17

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K1/18

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/181 ,  H05K1/182 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/10159 ,  H05K2201/10363 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board including a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on one surface of the first substrate and including multiple interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including multiple conductive circuits for being connected to multiple semiconductor elements, and a filler filling the opening portion of the built-up layer such that the interposer is held in the opening portion of the built-up layer. The opening portion of the built-up layer has a tapered portion tapering toward the outermost surface of the built-up layer.

Abstract translation: 一种布线基板，包括具有穿透所述第一基板的穿透孔的第一基板，形成在所述第一基板的一个表面上并且包括多个层间树脂绝缘层和布线层的积层，所述积层具有开口部 与第一基板的贯通孔相通并且向组合层的最外表面开口，插入物容纳在积层的开口部分中，并且包括形成在第二基板上的第二基板和布线层， 插入器的布线层包括用于连接到多个半导体元件的多个导电电路，以及填充积层的开口部分的填充物，使得插入器被保持在积层的开口部分中。 积层的开口部分具有朝向堆积层的最外表面渐缩的锥形部分。

公开(公告)号：US20140033526A1

公开(公告)日：2014-02-06

申请号：US14052443

申请日：2013-10-11

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Tsung-Yuan Chen ,  Ming-Huang Ting

IPC: H05K3/40

CPC classification number: H05K3/4007 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68304 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/2919 ,  H01L2224/321 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81903 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4614 ,  H05K3/4647 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49124 ,  Y10T29/49128 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A fabricating method of an embedded package structure includes following steps. First and second boards are combined to form an integrated panel. First and second circuit structures are respectively formed on the first and second boards that are then separated. An embedded element is electrically disposed on the first circuit structure. First and second conductive bumps are respectively formed on a conductive circuit substrate and the second circuit structure. First and second semi-cured films are provided; a laminating process is performed to laminate the first circuit structure on the first board, the first and second semi-cured films, the conductive circuit substrate, and the second circuit structure on the second board. The first and second semi-cured films encapsulate the embedded element. The first and second conductive bumps respectively pierce through the first and second semi-cured films and are electrically connected to the first circuit structure and the conductive circuit substrate, respectively.

Abstract translation: 嵌入式封装结构的制造方法包括以下步骤。 第一和第二板组合形成集成面板。 第一和第二电路结构分别形成在第一和第二板上，然后分离。 嵌入式元件电气地布置在第一电路结构上。 第一和第二导电凸块分别形成在导电电路基板和第二电路结构上。 提供第一和第二半固化膜; 执行层压工艺以将第一板上的第一电路结构，第二和第二半固化膜，导电电路基板和第二电路结构层叠在第二板上。 第一和第二半固化膜封装了嵌入元件。 第一和第二导电凸块分别穿过第一和第二半固化膜，并分别电连接到第一电路结构和导电电路基板。

公开(公告)号：US08642897B2

公开(公告)日：2014-02-04

申请号：US13218968

申请日：2011-08-26

Applicant: Shunsuke Sakai

Inventor： Shunsuke Sakai

IPC: H05K1/16

CPC classification number: H01L24/24 ,  H01L21/568 ,  H01L23/145 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/3511 ,  H05K1/185 ,  H05K2201/10674 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A wiring board including a core substrate having an accommodation portion, an electronic component in the accommodation portion having a substrate, a resin layer on a surface of the substrate and an electrode on the resin layer, a first interlayer resin insulation layer on a surface of the core substrate and a surface of the substrate of the component, and a second interlayer resin insulation layer on the opposite surface of the core substrate and a surface of the substrate having the resin layer and electrode. The first insulation layer has resin in the amount greater than the amount of resin in the second insulation layer such that the total amount of resin component including the resin in the first insulation layer is adjusted to be substantially the same as the total amount of resin component including the resin in the second insulation layer and resin in the resin layer.

Abstract translation: 一种布线板，包括具有容纳部的芯基板，具有基板的容纳部中的电子部件，基板的表面上的树脂层和树脂层上的电极，表面上的第一层间树脂绝缘层 核心基板和部件的基板的表面，以及在芯基板的相对表面上的第二层间树脂绝缘层和具有树脂层和电极的基板的表面。 第一绝缘层具有比第二绝缘层中的树脂量大的树脂，使得包含第一绝缘层中的树脂的树脂成分的总量被调节为与树脂成分的总量基本相同 包括第二绝缘层中的树脂和树脂层中的树脂。

公开(公告)号：US08633396B2

公开(公告)日：2014-01-21

申请号：US12714077

申请日：2010-02-26

Applicant: Eung Suek Lee ,  Jee Soo Mok ,  Jun Oh Hwang

Inventor： Eung Suek Lee ,  Jee Soo Mok ,  Jun Oh Hwang

IPC: H05K1/09

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/1132 ,  H01L2224/11901 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/321 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed is a die mounting substrate, which includes a mounting substrate having a pad, a die having a terminal and surface-mounted on the mounting substrate, and a conductive paste bump formed on the pad or the terminal so as to connect the pad and the terminal to each other. When the die is connected and mounted on the mounting substrate using the conductive paste bump, shear stress is relieved thus preventing reliability from decreasing due to a difference in the coefficient of thermal expansion between the die and the mounting substrate, and also preventing the force of adhesion of the bump from decreasing due to the reduction in size of the pad of the mounting substrate.

Abstract translation: 公开了一种管芯安装基板，其包括具有焊盘的安装基板，具有端子并且表面安装在安装基板上的管芯，以及形成在焊盘或端子上的导电焊膏，以便将焊​​盘和 终端彼此。 当使用导电膏凸点将管芯连接并安装在安装基板上时，解除剪切应力，从而防止由于管芯和安装基板之间的热膨胀系数的差异导致的可靠性降低，并且还防止 由于安装基板的焊盘的尺寸的减小，凸块的粘附性降低。

公开(公告)号：US20140009899A1

公开(公告)日：2014-01-09

申请号：US14033695

申请日：2013-09-23

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Satoshi ITO ,  Yoichi MORIYA ,  Tetso KANAMORI ,  Yukihiro YAGI ,  Yuki YAMAMOTO

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K1/18

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/18 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/181 ,  H05K1/188 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/0323 ,  H05K2203/1476

Abstract: A wiring substrate includes an insulating layer, an upper wiring pattern, and a lower wiring pattern, the wiring patterns sandwiching the insulating layer. The lower wiring pattern includes an interlayer connecting conductor integral therewith and projecting toward the upper wiring pattern for electrical connection to the upper wiring pattern. The interlayer connecting conductor is joined to the upper wiring pattern so as to penetrate into the upper wiring pattern beyond a joining interface between the insulating layer and the upper wiring pattern. Thus, the wiring substrate adaptable for a large current is provided without causing degradation of reliability in connection, which may occur by cracking, disconnection, interlayer peeling-off, etc.

Abstract translation: 布线基板包括绝缘层，上布线图案和下布线图案，布线图案夹着绝缘层。 下布线图案包括与其一体的层间连接导体，并朝向上布线图案突出以与上布线图形电连接。 层间连接导体与上部布线图案接合，以便在绝缘层和上部布线图案之间的接合界面之外穿透上部布线图案。 因此，可以提供适合于大电流的布线基板，而不会由于断裂，断开，层间剥离等而导致连接可靠性的劣化。

公开(公告)号：US20140008814A1

公开(公告)日：2014-01-09

申请号：US13895704

申请日：2013-05-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。