公开(公告)号：US20170186660A1

公开(公告)日：2017-06-29

申请号：US15457736

申请日：2017-03-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： See Chian Lim ,  Teck Tiong Tan ,  Yung Kuan Hsiao ,  Ching Meng Fang ,  Yoke Hor Phua ,  Bartholomew Liao

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/15 ,  H01L21/768 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/145 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/11

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

公开(公告)号：US20170148721A1

公开(公告)日：2017-05-25

申请号：US15428007

申请日：2017-02-08

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

公开(公告)号：US09659897B1

公开(公告)日：2017-05-23

申请号：US15167895

申请日：2016-05-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Zigmund Ramirez Camacho ,  Emmanuel Espiritu ,  Bartholomew Liao Chung Foh ,  Dao Nguyen Phu Cuong ,  Jeffrey David Punzalan

IPC: H01L23/22 ,  H01L23/24 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L24/25 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/17 ,  H01L25/04 ,  H01L2224/16225 ,  H01L2224/1701 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.

公开(公告)号：US20170110599A1

公开(公告)日：2017-04-20

申请号：US15394337

申请日：2016-12-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L31/0203 ,  H01L27/146 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L31/0203 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14698 ,  H01L31/02005 ,  H01L31/1876 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4038 ,  H05K2203/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.

公开(公告)号：US20170069565A1

公开(公告)日：2017-03-09

申请号：US15257770

申请日：2016-09-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： BONG WOO CHOI ,  SUNGSOO KIM ,  HYUNGSANG PARK ,  JIWON JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/4803 ,  H01L21/4846 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Approaches, techniques, and mechanisms are disclosed for a method of manufacturing an integrated circuit package with a single-layer substrate. In an embodiment, the inventive integrated circuit package not only reduces manufacture cost but also improves reliability and miniaturization. According to an embodiment, a single-layer substrate is manufactured using non-photoimageable dielectric (NPID) material that is different from other dielectric materials, such as PrePreg (PPG) materials, copper clad laminates (CCL), solder resists (SR), and so forth, that are used in conventional substrates. A single-layer substrate manufactured using the NPID material provides a low cost solution by, among other aspects, eliminating certain process steps, such as a laser drill process, that are often used to manufacture the other substrates. According to an embodiment, the NPID material utilized for the described techniques and systems may feature a low coefficient of thermal expansion (CTE), a high glass transition temperature (Tg), and/or a high modulus compared to the other dielectric materials. Such features improve reliability because of, among other aspects, improved trace protection and peel strength, thereby enhancing adhesion between traces (e.g., of copper (Cu), etc.) and dielectric materials. In an embodiment, such features also improve miniaturization because, for example, the NPID material may allow formation of traces with reduced geometry.

Abstract translation: 公开了用于制造具有单层衬底的集成电路封装的方法的方法，技术和机制。 在一个实施例中，本发明的集成电路封装不仅降低了制造成本，而且还提高了可靠性和小型化。 根据实施例，使用不同于其它介电材料的不可光成像的电介质（NPID）材料制造单层基板，例如PrePreg（PPG）材料，覆铜层压板（CCL），阻焊剂（SR）， 等等，其用于常规基板。 使用NPID材料制造的单层基材通过除其他方面提供了低成本的解决方案，消除了常用于制造其它基材的某些工艺步骤，例如激光钻孔工艺。 根据一个实施方案，用于所述技术和系统的NPID材料与其它电介质材料相比具有低的热膨胀系数（CTE），高玻璃化转变温度（Tg）和/或高模量。 这些特征提高了可靠性，因为除了其它方面之外，还提供了改进的迹线保护和剥离强度，从而增强迹线（例如铜（Cu）等）和电介质材料之间的粘附。 在一个实施例中，这样的特征也改善了小型化，因为例如，NPID材料可以允许形成几何形状减小的迹线。

公开(公告)号：US20170062390A1

公开(公告)日：2017-03-02

申请号：US15349838

申请日：2016-11-11

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza A. Pagaila

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L21/288 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/17 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L29/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Abstract translation: 半导体器件具有在载体上形成的导电柱。 第一半导体管芯安装在载体之间的导电柱之间。 密封剂沉积在第一半导体管芯和载体上并且围绕导电柱。 在第一半导体管芯上的密封剂的第一表面中形成凹部。 凹槽有倾斜或阶梯。 在密封剂的第一表面上形成第一互连结构。 第一互连结构遵循密封剂中的凹部的轮廓。 载体被移除。 在密封剂和第一半导体管芯的第二表面上形成第二互连结构。 第一和第二互连结构电连接到导电柱。 第二半导体管芯安装在凹槽中。 第三半导体管芯安装在凹槽和第二半导体管芯上。

公开(公告)号：US20160336299A1

公开(公告)日：2016-11-17

申请号：US15218847

申请日：2016-07-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi C. Marimuthu ,  Sheila Marie L. Alvarez ,  Yaojian Lin ,  Jose A. Caparas ,  Yang Kern Jonathan Tan

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/2633 ,  H01L21/311 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0558 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49174 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/94 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract translation: 半导体器件具有设置在衬底的第一表面上的衬底和半导体管芯。 线柱附接到基底的第一表面。 线螺柱包括基部和杆部。 在衬底的第二表面上形成焊盘。 密封剂沉积在衬底，半导体管芯和线螺柱上。 密封剂的一部分被LDA去除以暴露线螺柱。 通过LDA去除一部分密封剂以暴露基底。 互连结构形成在密封剂上并电连接到线芯和半导体管芯。 在互连结构上形成凸点。 半导体封装设置在密封剂上并电连接到衬底。 分立半导体器件设置在密封剂上并电连接到衬底。

公开(公告)号：US20250140730A1

公开(公告)日：2025-05-01

申请号：US18498494

申请日：2023-10-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Linda Pei Ee Chua ,  DanFeng Yang ,  Hin Hwa Goh

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01Q1/22

Abstract: A semiconductor device has an electrical component and a first interconnect structure disposed adjacent to the electrical component. The electrical component can be a direct metal bonded semiconductor die or a flipchip semiconductor die. The first interconnect structure can be an interposer unit or a conductive pillar. A split antenna is disposed over the electrical component and first interconnect structure. The split antenna has a first antenna section and a second antenna section with an adhesive material disposed between the first antenna section and second antenna section. A second interconnect structure is formed over the electrical component and first interconnect structure. The second interconnect structure has one or more conductive layers and insulating layers. The first interconnect structure and second interconnect structure provide a conduction path between the electrical component and split antenna. An encapsulant is deposited around the electrical component and first interconnect structure.

公开(公告)号：US20250125289A1

公开(公告)日：2025-04-17

申请号：US18827895

申请日：2024-09-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KaiChong CHAN ,  PeiEe Linda CHUA ,  Yaojian LIN

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An integrated package and a method for making the same are provided. The integrated package includes: an antenna module including: an antenna module substrate; and a top antenna structure disposed on the antenna module substrate; a first encapsulant encapsulating the antenna module; a first redistribution structure disposed on a bottom surface of the first encapsulant, wherein the first redistribution structure includes a bottom antenna structure configured for coupling electromagnetic energy with the top antenna structure; and a semiconductor chip mounted on a bottom surface of the first redistribution structure and electrically coupled with the bottom antenna structure.

公开(公告)号：US12266615B2

公开(公告)日：2025-04-01

申请号：US18174790

申请日：2023-02-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L21/033 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.