公开(公告)号：US20040127008A1

公开(公告)日：2004-07-01

申请号：US10613459

申请日：2003-07-03

Inventor： Wilhelm Frey ,  Franz Laermer ,  Christoph Duenn

IPC: H01L021/28

CPC classification number: B81C1/00571 ,  B81C1/00595 ,  B81C2201/0133 ,  B81C2201/016 ,  B81C2203/0735 ,  C23F1/14 ,  H01L21/30604

Abstract: A method for producing a microsystem that has, situated on a substrate, a first functional layer that includes a conductive area and a sublayer. Situated on the first functional layer is a second mechanical functional layer, which is first initially applied onto a sacrificial layer situated and structured on the first functional layer. In addition, a layer is situated on the side of the sublayer facing away from the conductive area. The layer constitutes a protective layer on the first functional layer that acts in areas during a sacrificial layer etching process so that during removal of the sacrificial layer no etching of the areas of the first functional layer covered by the protective layer occurs, and that in the region of the areas of the first functional layer implemented without the protective layer the sublayer is removed essentially selectively to the conductive area at the same time as the sacrificial layer. Further, a method is described for producing integrated microsystems having silicon-germanium functional layers, sacrificial layers containing germanium, and open metal surfaces. The sacrificial layers containing germanium are at least partially removed in an etching solution, a pH value of the etching solution being kept at least approximately neutral during the etching procedure using a buffer.

Abstract translation: 一种微系统的制造方法，其具有位于基板上的包括导电区域和子层的第一功能层。 位于第一功能层上的是第二机械功能层，其首先被初始施加到位于第一功能层上并构成的牺牲层上。 此外，层位于子层背离导电区域的一侧。 该层在第一功能层上构成保护层，其在牺牲层蚀刻工艺期间在区域中起作用，使得在去除牺牲层期间不会发生由保护层覆盖的第一功能层的区域的蚀刻， 在没有保护层的情况下实现的第一功能层的区域的区域在与牺牲层同时基本上选择性地去除导电区域。 此外，描述了一种用于制造具有硅 - 锗功能层，包含锗的牺牲层和开放金属表面的集成微系统的方法。 在蚀刻溶液中至少部分地除去含有锗的牺牲层，在使用缓冲液的蚀刻过程中，蚀刻溶液的pH值保持至少大致为中性。

公开(公告)号：US06706549B1

公开(公告)日：2004-03-16

申请号：US10124689

申请日：2002-04-12

Applicant: Robert S. Okojie

Inventor： Robert S. Okojie

IPC: H01L2100

CPC classification number: B81C1/00182 ,  B81B2201/0235 ,  B81C2201/0133 ,  G01P2015/084

Abstract: A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiC wafer may be also be etched.

Abstract translation: 公开并要求保护大量SiC传感器的方法。 SiC以外的材料可以用作基板材料。 还公开并要求保护要求穿透SiC衬底的传感器。 采用工艺流程逆转，由此首先在将凹槽蚀刻入或通过晶片之前施加金属化。 铝沉积在金属化的整个平面上。 将光致抗蚀剂旋转到铝的基本平坦的表面上，随后被掩蔽（并显影和除去）。 用TMAH水溶液蚀刻不需要的铝，随后金属化被干蚀刻。 将光致抗蚀剂旋转到铝和氧化物的仍然基本上平坦的表面上，然后掩蔽（并显影和除去），留下未加蚀刻的光致抗蚀剂。 接下来，将ITO施加在铝，氧化物和未牺牲光致抗蚀剂的仍然基本平坦的表面上。 用丙酮除去其上直接上方的无定影和曝光的光致抗蚀剂和ITO。 接下来，深层反应离子蚀刻暴露了不受ITO保护的氧化物。 最后，热磷酸去除Al和ITO使电线与金属化连接。 也可以对SiC晶片的背面进行蚀刻。

公开(公告)号：US06642154B2

公开(公告)日：2003-11-04

申请号：US09900300

申请日：2001-07-05

Applicant: Jeffrey J. Peterson ,  Charles E. Hunt

Inventor： Jeffrey J. Peterson ,  Charles E. Hunt

IPC: H01L21302

CPC classification number: H01L21/30604 ,  B81C1/00626 ,  B81C2201/0104 ,  B81C2201/0133 ,  H01L21/30608

Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.

Abstract translation: 本发明的一个实施例提供了一种在半导体制造期间选择性蚀刻的方法。 该过程开始于接收由第一材料构成的第一层的硅衬底，第一层由第二材料构成的第二层覆盖。 然后，该过程执行蚀刻一些但不是全部第二层的第一蚀刻操作，使得第二层的一部分保持覆盖第一层。 接下来，系统执行第二蚀刻操作以选择性地使用选择性蚀刻剂蚀刻穿过第二层的剩余部分。 通过第二材料的选择性蚀刻剂的蚀刻速度比通过第一材料的选择性蚀刻剂的蚀刻速度快，使得第二蚀刻操作蚀刻穿过第二层的剩余部分并停止在第一层。

公开(公告)号：US20020123232A1

公开(公告)日：2002-09-05

申请号：US09683692

申请日：2002-02-04

Inventor： Tsung-Ping Hsu ,  In-Yao Lee ,  Hung-Sheng Hu ,  Chung-Cheng Chou ,  Wei-Lin Chen

IPC: H01L021/302 ,  H01L021/461

CPC classification number: B81C1/00626 ,  B81C2201/0133 ,  B81C2201/016

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layerand a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract translation: 用于高密度晶片生产的渐变蚀刻方法。 分级蚀刻方法分别作用于具有基板的顶表面和底表面上的第一钝化层和第二钝化层的基板上。 执行第一蚀刻工艺以同时蚀刻衬底和第一钝化层以去除第一钝化层。 最后，执行第二蚀刻工艺以将衬底蚀刻到用于在第二蚀刻工艺之后控制晶片的厚度的指定深度。

公开(公告)号：US06379573B1

公开(公告)日：2002-04-30

申请号：US09352582

申请日：1999-07-13

Applicant: Eun Sok Kim ,  Cheol-Hyun Han

Inventor： Eun Sok Kim ,  Cheol-Hyun Han

IPC: B44C122

CPC classification number: C03C15/00 ,  B81B2203/0315 ,  B81B2203/0376 ,  B81C1/00626 ,  B81C2201/0133 ,  H01L21/30604 ,  H01L21/3081 ,  Y10T428/2848

Abstract: During the formation of a spherical cavity in a substrate, self-limiting etching behavior of an isotropic etchant can be utilized when a tape is used as an etch mask. Such a self-limiting behavior is due to the presence of gas bubbles (consisted of SiF4 and NO, etch by-products) which close the etch window and limit the mass transport of the etchant to this silicon surface. Because of that, the spherical cavity size depends mostly on the size of the etch-mask opening, and is independent of the etching time. This self-limiting etching behavior precisely controls the dimension and uniformity of the spherical cavity.

Abstract translation: 在衬底中形成球形腔时，当使用带作为蚀刻掩模时，可以利用各向同性蚀刻剂的自限蚀刻行为。 这种自限制性行为是由于存在气泡（由SiF 4和NO（蚀刻副产物组成）），其关闭蚀刻窗口并限制蚀刻剂对该硅表面的质量传递。 因此，球形腔尺寸主要取决于蚀刻掩模开口的尺寸，并且与蚀刻时间无关。 这种自限制蚀刻行为精确地控制球形腔的尺寸和均匀性。

公开(公告)号：US06342427B1

公开(公告)日：2002-01-29

申请号：US09473968

申请日：1999-12-29

Applicant: Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

Inventor： Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

IPC: H01L2100

CPC classification number: B81C1/00047 ,  B81B2203/033 ,  B81C2201/0133 ,  B81C2201/0178 ,  B81C2203/0136

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract translation: 公开了一种用于形成微腔的方法。 在形成空腔的方法中，在硅层上形成第一层，并且通过选择性地蚀刻硅层，在硅层中形成沟槽。 在沟槽和硅层上形成第二和第三层。 通过部分地蚀刻第三层，通过第三层形成蚀刻孔。 在通过蚀刻孔除去第二层之后，在硅层和第三层之间形成空穴。 因此，通过利用硅或多晶硅层的体积膨胀，可以容易地在硅层中形成并密封具有大尺寸的空腔。 此外，可以根据在热氧化处理后部分打开的蚀刻孔上形成的低真空CVD氧化物层或氮化物层，通过控制与聚合物的其它部分相关的蚀刻孔的尺寸，形成真空微腔 硅层。

公开(公告)号：US6124214A

公开(公告)日：2000-09-26

申请号：US141144

申请日：1998-08-27

Applicant: David R. Hembree ,  Salman Akram

Inventor： David R. Hembree ,  Salman Akram

IPC: H01L21/00 ,  H01L21/302

CPC classification number: B81C1/00539 ,  B81C1/00626 ,  B81C99/004 ,  B81B2207/07 ,  B81C2201/0133 ,  G01R1/06738 ,  G01R3/00 ,  H01L21/30608

Abstract: Methods of forming substantially defect-free silicon structures at the submicron level by enhancing microscopic etchant concentration uniformity and reducing hydrogen bubble adhesion. Etchant mixtures are subjected to the application of ultrasonic waves. The ultrasonic waves promote cavitation that mixes the etchant mixture on a microscopic level, and also assists in promoting bubble detachment. Wetting agents are added to the etchant mixture to enhance the hydrophilicity of the silicon surfaces and thereby reduce bubble adhesion. Apparatus to carry out the method of forming silicon structures are also disclosed.

Abstract translation: 通过增强微观腐蚀剂浓度均匀性和降低氢气粘附力，在亚微米级别形成基本上无缺陷的硅结构的方法。 蚀刻剂混合物经受超声波的应用。 超声波促进空化，将蚀刻剂混合物在微观层面上混合，并且还有助于促进气泡分离。 将润湿剂加入到蚀刻剂混合物中以增强硅表面的亲水性，从而降低气泡附着力。 还公开了进行形成硅结构的方法的设备。

公开(公告)号：US5594172A

公开(公告)日：1997-01-14

申请号：US540613

申请日：1990-06-20

Applicant: Toshiro Shinohara

Inventor： Toshiro Shinohara

IPC: G01P15/08 ,  G01P15/12

CPC classification number: G01P15/0802 ,  B81C1/00595 ,  B81B2201/025 ,  B81B2203/0118 ,  B81C2201/0133 ,  G01P2015/0828

Abstract: A semiconductor accelerometer, including a weight and a cantilevered beam formed in a silicon semiconductor substrate as a frame having a (100) surface, and a strain sensing device formed in a surface portion near a support portion of the cantilevered beam, the silicon cantilevered beam having a triangular cross section defined by one (100) surface and two (111) surfaces or a pentagonal cross section defined by one (100) surface, two (110) surfaces and two (111) surfaces. A method for producing the semiconductor accelerometer is also disclosed.

Abstract translation: 一种半导体加速度计，其包括形成在具有（100）表面的框架的硅半导体衬底中的重量和悬臂梁，以及形成在悬臂梁的支撑部附近的表面部分中的应变感测装置，所述硅悬臂梁 具有由一个（100）表面和两个（111）表面限定的三角形横截面或由一个（100）表面，两个（110）表面和两个（111）表面限定的五边形横截面。 还公开了一种用于制造半导体加速度计的方法。

公开(公告)号：US20240359969A1

公开(公告)日：2024-10-31

申请号：US18770886

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Tao-Cheng Liu ,  Ying-Hsun Chen ,  Chen-Hsuan Yen

IPC: B81B3/00 ,  B81C1/00 ,  G01P1/00 ,  G01P15/08

CPC classification number: B81B3/007 ,  B81C1/00658 ,  G01P1/00 ,  G01P15/08 ,  B81B2201/0235 ,  B81B2203/0136 ,  B81B2203/04 ,  B81C2201/0133 ,  B81C2201/0181

Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.

公开(公告)号：US12122665B2

公开(公告)日：2024-10-22

申请号：US17459253

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Tao-Cheng Liu ,  Chen-Hsuan Yen ,  Ying-Hsun Chen

IPC: B81B3/00 ,  B81C1/00 ,  G01P1/00 ,  G01P15/08

CPC classification number: B81B3/007 ,  B81C1/00658 ,  G01P1/00 ,  G01P15/08 ,  B81B2201/0235 ,  B81B2203/0136 ,  B81B2203/04 ,  B81C2201/0133 ,  B81C2201/0181

Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.