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1.发明公开公开(公告)号：US20240359969A1
公开(公告)日：2024-10-31
申请号：US18770886
申请日：2024-07-12
Inventor： Tao-Cheng Liu , Ying-Hsun Chen , Chen-Hsuan Yen
CPC classification number: B81B3/007 , B81C1/00658 , G01P1/00 , G01P15/08 , B81B2201/0235 , B81B2203/0136 , B81B2203/04 , B81C2201/0133 , B81C2201/0181
Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.
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2.发明授权公开(公告)号：US12122665B2
公开(公告)日：2024-10-22
申请号：US17459253
申请日：2021-08-27
Inventor： Tao-Cheng Liu , Chen-Hsuan Yen , Ying-Hsun Chen
CPC classification number: B81B3/007 , B81C1/00658 , G01P1/00 , G01P15/08 , B81B2201/0235 , B81B2203/0136 , B81B2203/04 , B81C2201/0133 , B81C2201/0181
Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.
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公开(公告)号：US20240280513A1
公开(公告)日：2024-08-22
申请号：US18224325
申请日：2023-07-20
Inventor： Jae Hong LEE , Jungwon PARK , Min-Ho KANG , Minyoung LEE , Hyeong Seok JANG , Won Jong JUNG , Jin Ha KIM , Kak NAMKOONG , Hyung Jun YOUN
IPC: G01N23/06 , B81B1/00 , B81C1/00 , G01N33/483
CPC classification number: G01N23/06 , B81B1/002 , B81C1/00071 , G01N33/483 , B81B2201/05 , B81B2203/033 , B81B2203/0338 , B81C2201/0132 , B81C2201/0181 , B81C2201/0198
Abstract: The present disclosure provides methods and apparatuses for biomaterial detection sensors. In some embodiments, a biomaterial detection sensor includes a membrane including a plurality of wells. Each of the plurality of wells is configured to encapsulate a biomaterial contained in a sample solution. A surface of the membrane is selectively modified into at least one of a hydrophilic surface and a hydrophobic surface. In some embodiments, a method of manufacturing a biomaterial detection sensor includes depositing a first membrane and a second membrane on respective surfaces of a wafer, forming a window by etching the first membrane and the first surface of the wafer, forming a plurality of wells on the second membrane, modifying a surface of the second membrane into at least one of a hydrophilic surface and a hydrophobic surface; and transferring a two-dimensional graphene oxide material onto a bottom of each of the plurality of wells.
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公开(公告)号：US11851321B2
公开(公告)日：2023-12-26
申请号：US17188933
申请日：2021-03-01
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ting-Li Yang , Kai-Di Wu , Ming-Da Cheng , Wen-Hsiung Lu , Cheng Jen Lin , Chin Wei Kang
CPC classification number: B81B3/0081 , B81C1/0069 , B81B2203/019 , B81B2203/0127 , B81B2203/0353 , B81B2207/015 , B81C2201/013 , B81C2201/0181 , B81C2203/032 , B81C2203/0735
Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.
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公开(公告)号：US11851320B2
公开(公告)日：2023-12-26
申请号：US16609968
申请日：2018-05-01
Applicant: THE JOHNS HOPKINS UNIVERSITY
Inventor： Gi-Dong Sim , Jessica Krogstad , Timothy P. Weihs , Kevin J. Hemker , Gianna Valentino
CPC classification number: B81B3/0075 , B81C1/00674 , C23C14/18 , C23C14/5806 , C25D3/562 , C25D5/50 , B81B2203/0118 , B81C2201/0132 , B81C2201/0133 , B81C2201/0181 , B81C2201/0197
Abstract: The present invention is directed to the synthesis of metallic nickel-molybdenum-tungsten films and coatings with direct current sputter deposition, which results in fully-dense crystallographically textured films that are filled with nano-scale faults and twins. The as-deposited films exhibit linear-elastic mechanical behavior and tensile strengths above 2.5 GPa, which is unprecedented for materials that are compatible with wafer-level device fabrication processes. The ultra-high strength is attributed to a combination of solid solution strengthening and the presence of the dense nano-scale faults and twins. These films also possess excellent thermal and mechanical stability, high density, low CTE, and electrical properties that are attractive for next generation metal MEMS applications. Deposited as coatings these films provide protection against friction and wear. The as-deposited films can also be heat treated to modify the internal microstructure and attendant mechanical properties in a way that provides a desired balance of strength and toughness.
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Patent Agency Ranking
公开(公告)号：US20230278856A1
公开(公告)日：2023-09-07
申请号：US18315799
申请日：2023-05-11
Applicant: Taiwan Semiconductor manufacturing Co., Ltd.
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81C1/00246 , B81B7/0051 , B81B2201/0264 , B81B2201/0271 , B81B2201/0257 , B81C2203/0714 , B81C2201/112 , B81C2201/0176 , B81C2201/0181 , B81C2201/0132 , B81C2201/0133 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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公开(公告)号：US09975754B2
公开(公告)日：2018-05-22
申请号：US15498009
申请日：2017-04-26
Inventor： Fu-Chun Huang , Li-Chen Yen , Tzu-Heng Wu , Yi-Heng Tsai , Chun-Ren Cheng
CPC classification number: B81B3/0086 , B81B3/0008 , B81B2203/0307 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C2201/0132 , B81C2201/0181 , B81C2203/035
Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.
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8.发明授权公开(公告)号：US09643179B1
公开(公告)日：2017-05-09
申请号：US15192281
申请日：2016-06-24
Applicant: International Business Machines Corporation
Inventor： Sebastian U. Engelmann , Stephen M. Rossnagel , Ying Zhang
IPC: G01N27/403 , B01L3/00 , B82B1/00 , B82B3/00
CPC classification number: G01N27/4146 , B01L3/502707 , B01L3/502761 , B01L2200/0663 , B01L2300/0861 , B01L2300/0887 , B01L2300/0896 , B81B2201/051 , B81C1/00119 , B81C2201/0181 , B82B1/005 , B82B3/008 , G01N27/4145 , G01N33/48721
Abstract: Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.
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公开(公告)号：US20160264410A1
公开(公告)日：2016-09-15
申请号：US15162997
申请日：2016-05-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Michael T. Brigham , Christopher V. Jahnes , Cameron E. Luce , Jeffrey C. Maling , William J. Murphy , Anthony K. Stamper , Eric J. White
IPC: B81C1/00
CPC classification number: B81C1/0015 , B81B3/0021 , B81B2203/0118 , B81B2203/0315 , B81B2207/09 , B81C1/00047 , B81C1/00269 , B81C1/00365 , B81C1/00531 , B81C1/00936 , B81C2201/0104 , B81C2201/0107 , B81C2201/0121 , B81C2201/0125 , B81C2201/0132 , B81C2201/0176 , B81C2201/0181 , B81C2203/0109 , B81C2203/0145 , B81C2203/0714 , G06F17/5009
Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.
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公开(公告)号：US20160233097A1
公开(公告)日：2016-08-11
申请号：US15007867
申请日：2016-01-27
Inventor： Robert W. Carpick , Frank Streller , Rahul Agarwal , Filippo Mangolini
IPC: H01L21/285 , C01B33/06 , H01L29/45 , H01L21/768 , B81C1/00 , B81B3/00
CPC classification number: H01L21/28518 , B81B3/0086 , B81B2201/01 , B81B2203/04 , B81C1/00698 , B81C2201/0181 , C01B33/06 , H01L29/456 , H01L29/84
Abstract: The disclosed subject matter provides thin films including a metal silicide and methods for forming such films. The disclosed subject matter can provide techniques for tailoring the electronic structure of metal thin films to produce desirable properties. In example embodiments, the metal silicide can comprise a platinum silicide, such as for example, PtSi, Pt2Si, or Pt3Si. For example, the disclosed subject matter provides methods which include identifying a desired phase of a metal silicide, providing a substrate, depositing at least two film layers on the substrate which include a first layer including amorphous silicon and a second layer including metal contacting the first layer, and annealing the two film layers to form a metal silicide. Methods can be at least one of a source-limited method and a kinetically-limited method. The film layers can be deposited on the substrate using techniques known in the art including, for example, sputter depositing.
Abstract translation: 所公开的主题提供了包括金属硅化物的薄膜和用于形成这种膜的方法。 所公开的主题可以提供用于定制金属薄膜的电子结构以产生期望特性的技术。 在示例性实施例中，金属硅化物可以包括铂硅化物，例如PtSi，Pt 2 Si或Pt 3 Si。 例如，所公开的主题提供了包括识别金属硅化物的期望相位，提供衬底，在衬底上沉积至少两个膜层的方法，该至少两个膜层包括包含非晶硅的第一层和包括与第一层接触的金属的第二层 层，并且退火两个膜层以形成金属硅化物。 方法可以是源限制方法和动力学限制方法中的至少一种。 可以使用本领域已知的技术将膜层沉积在基板上，包括例如溅射沉积。
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