METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FORMATION OF CHEMICAL GUIDE PATTERNS FOR DIRECTED SELF-ASSEMBLY LITHOGRAPHY
    161.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FORMATION OF CHEMICAL GUIDE PATTERNS FOR DIRECTED SELF-ASSEMBLY LITHOGRAPHY 有权
    用于制作集成电路的方法,包括形成用于方向自组装图的化学指南图案

    公开(公告)号:US20140273511A1

    公开(公告)日:2014-09-18

    申请号:US13841694

    申请日:2013-03-15

    Abstract: Methods for creating chemical guide patterns by DSA lithography for fabricating an integrated circuit are provided. In one example, an integrated circuit includes forming a bifunctional brush layer of a polymeric material overlying an anti-reflective coating on a semiconductor substrate. The polymeric material has a neutral polymeric block portion and a pinning polymeric block portion that are coupled together. The bifunctional brush layer includes a neutral layer that is formed of the neutral polymeric block portion and a pinning layer that is formed of the pinning polymeric block portion. A portion of the neutral layer or the pinning layer is selectively removed to define a chemical guide pattern. A block copolymer layer is deposited overlying the chemical guide pattern. The block copolymer layer is phase separated to define a nanopattern that is registered to the chemical guide pattern.

    Abstract translation: 提供了通过DSA光刻产生化学引导图案以制造集成电路的方法。 在一个示例中,集成电路包括形成覆盖半导体衬底上的抗反射涂层的聚合材料的双功能刷层。 聚合物材料具有中性聚合物嵌段部分和联结在一起的钉扎聚合物嵌段部分。 双功能刷层包括由中性聚合物嵌段部分形成的中性层和由钉扎聚合物嵌段部分形成的钉扎层。 选择性地去除中性层或钉扎层的一部分以限定化学引导图案。 沉积在化学引导图案上的嵌段共聚物层。 嵌段共聚物层被相分离以限定与化学引导图案对应的纳米图案。

    Method for forming pattern and mask pattern, and method for manufacturing semiconductor device
    162.
    发明授权
    Method for forming pattern and mask pattern, and method for manufacturing semiconductor device 有权
    用于形成图案和掩模图案的方法,以及制造半导体器件的方法

    公开(公告)号:US08828871B2

    公开(公告)日:2014-09-09

    申请号:US13293979

    申请日:2011-11-10

    Abstract: A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps.

    Abstract translation: 在本公开中提供了图案形成方法,掩模图案形成方法和半导体器件的制造方法,其涉及半导体工艺领域。 图案形成方法包括:提供基板; 在基材上形成含有嵌段共聚物的聚合物薄膜; 通过用印模压印聚合物薄膜来形成第一图案; 通过在第一图案中共聚物的定向自组装形成由不同共聚物组分组成的畴; 选择性地除去由共聚物组分组成的畴以形成第二图案。 在本发明的实施例中,可以通过组合压印和DSA处理而不曝光来获得更细的间距图案,与现有技术的方法相比,其简单性优点。 此外,在印记中使用的邮票可以具有相对更大的间距,便于和简化邮票的制造和对准。

    DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS USING LASER ANNEALING
    164.
    发明申请
    DIRECTED SELF-ASSEMBLY OF BLOCK COPOLYMERS USING LASER ANNEALING 有权
    使用激光退火的嵌段共聚物的自制自组装

    公开(公告)号:US20140106575A1

    公开(公告)日:2014-04-17

    申请号:US13653606

    申请日:2012-10-17

    Inventor: Kenji YOSHIMOTO

    Abstract: Methods for performing directed self-assembly (DSA) of block copolymer (BCP) material on a substrate are disclosed. The BCP is disposed over a patterned neutral layer made from a random copolymer. The BCP is annealed with a laser to induce the directed self-assembly. The scan type may include single scan, multiple scan, or multiple scan with overlap. A variety of power settings and dwell times may be used within a single wafer to achieve multiple heating conditions within a single wafer.

    Abstract translation: 公开了在基片上进行嵌段共聚物(BCP)材料的定向自组装(DSA)的方法。 BCP布置在由无规共聚物制成的图案化中性层上。 BCP用激光退火以诱导定向自组装。 扫描类型可能包括单次扫描,多次扫描或重叠扫描。 可以在单个晶片内使用各种功率设置和停留时间来实现单个晶片内的多个加热条件。

    Method for producing reconfigurable microchannels
    165.
    发明授权
    Method for producing reconfigurable microchannels 失效
    生产可重构微通道的方法

    公开(公告)号:US08679423B2

    公开(公告)日:2014-03-25

    申请号:US12988213

    申请日:2009-04-23

    Applicant: Yves Fouillet

    Inventor: Yves Fouillet

    Abstract: A microfluidic device, including a microfluidic network, including: a) two parallel plates each including one or more electrodes, b) at least one channel, arranged between the two plates, made from a material obtained by solidification or hardening of a material of a first fluid, and c) a mechanism varying a physical parameter of the material constituting walls of the channel so as to cause the material to pass at least from the liquid state to the solid state.

    Abstract translation: 包括微流体网络的微流体装置,包括:a)两个平行板,每个平行板包括一个或多个电极,b)布置在两个板之间的至少一个通道,由通过固化或硬化材料获得的材料制成 第一流体,以及c)改变通道的材料构成壁的物理参数以使材料至少从液态通过至固态的机构。

    METHOD OF FORMING FINE PATTERN, AND DEVELOPER
    166.
    发明申请
    METHOD OF FORMING FINE PATTERN, AND DEVELOPER 有权
    形成精细图案的方法和开发者

    公开(公告)号:US20140054265A1

    公开(公告)日:2014-02-27

    申请号:US13927464

    申请日:2013-06-26

    Abstract: A method of forming a fine pattern, including: a phase separation step in which a layer containing a block copolymer having a plurality of blocks bonded is formed on a substrate, and then the layer is heated for phase separation of the layer; a decomposition step in which at least a portion of a phase of at least one block of the plurality of blocks constituting the block copolymer is decomposed; a selective removal step in which the layer is immersed in a developing solution to selectively remove a phase containing decomposed blocks to form a nano structure; and an etching step in which the substrate is subjected to etching by using the nano structure as a mask; and a main component of the developing solution is an organic solvent having an SP value of 7.5 to 11.5 (cal/cm3)1/2, and having vapor pressure of less than 2.1 kPa at 25° C., or is benzene that may be substituted by an alkyl group, an alkoxy group, or a halogen atom, and the developing solution further contains metal alkoxide.

    Abstract translation: 一种形成精细图案的方法,包括:相位分离步骤,其中在基板上形成含有多个键合的嵌段共聚物的层,然后将该层加热以使该层相分离; 分解步骤,其中构成所述嵌段共聚物的多个嵌段的至少一个嵌段的至少一部分相分解; 选择性去除步骤,其中将该层浸入显影溶液中以选择性地除去含有分解嵌段的相以形成纳米结构; 以及通过使用纳米结构作为掩模对基板进行蚀刻的蚀刻步骤; 显影液的主要成分是在25℃下SP值为7.5〜11.5(cal / cm 3)1/2,蒸气压小于2.1kPa的有机溶剂,也可以是苯 被烷基,烷氧基或卤素原子取代,显影液还含有金属醇盐。

    STANDARDIZED TOPOGRAPHICAL ARRANGEMENTS FOR TEMPLATE REGIONS THAT ORIENT SELF-ASSEMBLY
    168.
    发明申请
    STANDARDIZED TOPOGRAPHICAL ARRANGEMENTS FOR TEMPLATE REGIONS THAT ORIENT SELF-ASSEMBLY 有权
    标准化地理位置对于自由组合模式区域的地形安排

    公开(公告)号:US20130318483A1

    公开(公告)日:2013-11-28

    申请号:US13899936

    申请日:2013-05-22

    Abstract: This disclosure relates generally to systems and methods of providing standardized topographical configurations for template regions. In one embodiment, a set of array arrangements is selected. Arrays of template structures are then formed on at least one substrate. Each of the arrays is arranged in accordance with an array arrangement in the set of array arrangements such that the arrays correspond surjectively onto the set of array arrangements. After the arrays are formed, a self-assembly material is provided on the arrays. Self-assembly patterns formed by self-assembling material as a result of the arrays may be empirically observed and used to map a set of self-assembly pattern arrangements surjectively onto the set of array arrangements. Using this mapping, a combination of the self-assembly pattern arrangements that match a target pattern arrangement can be used to select a combination of array arrangements from the set of array arrangements for a template region.

    Abstract translation: 本公开一般涉及为模板区域提供标准化的外形配置的系统和方法。 在一个实施例中,选择一组阵列布置。 然后在至少一个基底上形成模板结构的阵列。 每个阵列根据阵列布置集合中的阵列布置被布置,使得阵列突出地对准阵列布置集合。 在形成阵列之后,在阵列上提供自组装材料。 可以凭经验观察自组装材料形成的自组装图案,并将其用于将一组自组装图案布置映射到阵列布置集合上。 使用该映射,可以使用与目标图案布置匹配的自组装图案布置的组合来从模板区域的阵列布置集合中选择阵列布置的组合。

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