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    PLUG AND METHOD FOR PRODUCING SAME
    163.
    发明申请
    PLUG AND METHOD FOR PRODUCING SAME 有权
    插片及其制造方法

    公开(公告)号：US20140199890A1

    公开(公告)日：2014-07-17

    申请号：US14127558

    申请日：2012-06-15

    Applicant: Dominik Schweizer

    Inventor： Dominik Schweizer

    IPC: H01R13/6463 ,  H01R43/26

    CPC classification number: H01R13/6463 ,  H01R13/035 ,  H01R13/6461 ,  H01R13/6466 ,  H01R24/64 ,  H01R43/18 ,  H01R43/26 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/09118 ,  Y10T29/49208

    Abstract: A plug for an electrical plug-type connector includes a plurality of plug contacts, which are electrically connected or connectable to a corresponding number of connecting elements, for example insulation displacement contacts, clamping contacts or possibly also soldered joints, each for connecting one electrical cable core. Per plug contact, one conductor is formed as a conductor track which is grown three-dimensionally on the surface of a plug body in the form of a cast plastics part and adheres there, and which both forms the plug contact and electrically connects the plug contact to the connecting element.

    Abstract translation: 用于电插塞式连接器的插头包括多个插头触点，它们电连接或连接到相应数量的连接元件，例如绝缘位移触头，夹紧触点或可能还有焊接接头，每个用于连接一个电缆 核心。 每个插塞接触，一个导体形成为导体轨道，该导体轨迹在铸塑件的形式的塞体的表面上三维地生长并粘附在那里，并且两者形成插头接触并电连接插头接触 连接元件。

    Photopatterning
    164.
    发明申请
    Photopatterning 审中-公开

    公开(公告)号：US20140004320A1

    公开(公告)日：2014-01-02

    申请号：US14004716

    申请日：2012-02-27

    Applicant: Philip Gareth Bentley ,  David Stephen Thomas

    Inventor： Philip Gareth Bentley ,  David Stephen Thomas

    IPC: G03F7/095 ,  G03F7/30 ,  G03F7/20

    CPC classification number: G03F7/0957 ,  G03F7/20 ,  G03F7/30 ,  G03F7/40 ,  G06F3/041 ,  G06F2203/04103 ,  H05K3/185 ,  H05K2201/0108 ,  H05K2201/0236 ,  Y10T428/24802

    Abstract: A photopatternable structure (10) comprises an optically transparent substrate (12) having first and second faces (14, 16), coated respectively with first and second photosensitive materials (18, 20), the coated substrate being opaque to electromagnetic radiation of one or more wavelengths to which the photosensitive materials are sensitive. In use, the faces (14, 16) are exposed (sequentially or simultaneously) to curing radiation to which the photosensitive materials are sensitive and to which the coated substrate is opaque, resulting in two sided photopatterning without through -cure occurring.

    Abstract translation: 光可图案化结构（10）包括具有分别涂覆有第一和第二感光材料（18,20）的第一和第二面（14,16）的光学透明基底（12），所述涂覆的基底对于电磁辐射是不透明的， 感光材料敏感的更多波长。 在使用中，面（14,16）暴露（顺序地或同时地）固化感光材料敏感的辐射，并且涂覆的基底不透明，导致双侧光图案化而不会发生固化。

    ELECTRONIC DEVICE HOUSING AND METHOD FOR MANUFACTURING THE SAME
    165.
    发明申请
    ELECTRONIC DEVICE HOUSING AND METHOD FOR MANUFACTURING THE SAME 有权
    电子设备外壳及其制造方法

    公开(公告)号：US20130321988A1

    公开(公告)日：2013-12-05

    申请号：US13709472

    申请日：2012-12-10

    Applicant: PO-FENG HO ,  SHI-JIE YAN

    Inventor： PO-FENG HO ,  SHI-JIE YAN

    IPC: H05K13/00 ,  H05K7/00

    CPC classification number: H05K13/00 ,  H01Q1/40 ,  H05K3/184 ,  H05K7/00 ,  H05K2201/0236 ,  H05K2201/0999

    Abstract: An electronic device housing includes a plastic substrate. The plastic substrate includes a first surface. The electronic device housing further includes an activating layer formed on the first surface. The activating layer contains metal powder. The activating layer defines a recessed portion. Some of the metal powder is partially exposed on the surface of the recessed portion. Some of metal powder is partially inserted into the plastic substrate corresponding to the recessed portion. The electronic device housing further includes an antenna layer formed on the recessed portion. The antenna layer is a metal layer. A method for manufacturing the electronic device housing is also disclosed.

    Abstract translation: 电子设备外壳包括塑料基板。 塑料基板包括第一表面。 电子设备壳体还包括形成在第一表面上的激活层。 活化层含有金属粉末。 激活层限定凹陷部分。 一些金属粉末部分露出在凹部的表面上。 一些金属粉末部分地插入到与凹部对应的塑料基板中。 电子设备壳体还包括形成在凹部上的天线层。 天线层是金属层。 还公开了一种用于制造电子设备外壳的方法。

    METHOD FOR SELECTIVELY METALLIZING A SUBSTRATE AND INTERCONNECT DEVICE PRODUCED BY THIS METHOD
    166.
    发明申请
    METHOD FOR SELECTIVELY METALLIZING A SUBSTRATE AND INTERCONNECT DEVICE PRODUCED BY THIS METHOD 审中-公开
    用于选择性地金属化该方法生产的基板和互连装置的方法

    公开(公告)号：US20120183793A1

    公开(公告)日：2012-07-19

    申请号：US13350871

    申请日：2012-01-16

    Applicant: Wolfgang John ,  Bernd Roesener

    Inventor： Wolfgang John ,  Bernd Roesener

    IPC: B05D3/06 ,  B32B15/08 ,  B05D3/12

    CPC classification number: C23C18/1641 ,  C23C18/204 ,  C23C18/30 ,  H05K1/0373 ,  H05K3/185 ,  H05K3/381 ,  H05K2201/0116 ,  H05K2201/0236 ,  H05K2201/09118 ,  H05K2203/107

    Abstract: A method for selectively metallizing a substrate having a significant content of a plastics material includes ablating a layer of the substrate close to a surface of the substrate in a region of the substrate to be metallized so as to provide access to an additive having at least one compound from a substance family of aluminosilicates that is incorporated in the plastics material and to open one of a pore or a pore structure of the aluminosilicates in the region of the substrate to be metallized. The substrate is metallized with no external current starting inside the pore or the pore structure so as to incorporate a precious metal in the substrate and then at an outer edge region of the pores so as to form a planar metallization layer on the surface of the substrate

    Abstract translation: 用于选择性地金属化具有塑料材料的显着含量的衬底的方法包括在待金属化的衬底的区域中烧蚀靠近衬底表面的衬底的层，以便提供对具有至少一个 化合物，其由掺入塑料材料中的铝硅酸盐的物质族组成，并且在待金属化的基底区域中打开铝硅酸盐的孔或孔结构中的一种。 衬底金属化，没有外部电流开始在孔或孔结构内部，以便在衬底中并入贵金属，然后在孔的外缘区域处并入，以便在衬底的表面上形成平面的金属化层

    METHOD FOR ELECTRIC CIRCUIT DEPOSITION
    167.
    发明申请
    METHOD FOR ELECTRIC CIRCUIT DEPOSITION 审中-公开
    电路沉积方法

    公开(公告)号：US20110292622A1

    公开(公告)日：2011-12-01

    申请号：US13132004

    申请日：2009-12-11

    Applicant: Arjan Hovestad ,  Roland Anthony Tacken ,  Hendrik Rendering ,  Hero Hendrik 't Mannetje

    Inventor： Arjan Hovestad ,  Roland Anthony Tacken ,  Hendrik Rendering ,  Hero Hendrik 't Mannetje

    IPC: H05K7/00 ,  H05K1/00 ,  B05D5/12 ,  H05K3/06 ,  B82Y99/00

    CPC classification number: H05K3/184 ,  C23C18/1605 ,  C23C18/1608 ,  C23C18/1872 ,  C23C18/31 ,  H05K3/182 ,  H05K2201/0236 ,  H05K2201/0257 ,  H05K2203/0108 ,  H05K2203/0713 ,  H05K2203/122 ,  H05K2203/1407

    Abstract: The invention is directed to a method for preparing a substrate with an electrically conductive pattern for an electric circuit, to the substrate with the electrically conductive pattern, and to a device comprising the substrate with the electrically conductive pattern.The method of the invention comprises (a) providing an electrically insulating or semiconductive substrate, which substrate comprises a distribution of nanoparticles of a first metal or alloy thereof; (b) applying a layer of an inhibiting material onto said substrate, and locally removing or deactivating, light-induced, thermally, chemically and/or electrochemically, the layer of inhibiting material and thereby exposing at least part of the first metal or alloy thereof so as to obtain a pattern for an electric circuit; (c) depositing by means of an electroless process a layer of a second metal or alloy thereof on the exposed part of the first metal or alloy thereof present in the substrate as obtained in step (b), whereby inhibiting material that is still present on the substrate after step (b) locally inhibits the second metal or alloy thereof to be deposited on the first metal or alloy thereof, ensuring that the second metal or alloy thereof will selectively be deposited on the exposed part of the first metal or alloy thereof as obtained in step (b).

    Abstract translation: 本发明涉及一种用于制备具有用于电路的导电图案，具有导电图案的衬底以及包括具有导电图案的衬底的器件的衬底的方法。 本发明的方法包括（a）提供电绝缘或半导体衬底，该衬底包括第一金属或其合金的纳米颗粒的分布; （b）将一层抑制材料施加到所述基底上，并且将光诱导的，热的，化学的和/或电化学的方法局部去除或者化学地抑制所述抑制材料层，从而暴露其第一金属或其合金的至少一部分 以获得电路图案; （c）在步骤（b）中获得的在基板上存在的第一金属或其合金的暴露部分上通过无电镀方法沉积第二金属或其合金层，由此抑制仍然存在的材料 步骤（b）之后的基板局部地抑制第二金属或其合金沉积在第一金属或其合金上，确保其第二金属或合金将选择性地沉积在第一金属或其合金的暴露部分上，作为 在步骤（b）中获得。

    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL
    169.
    发明申请
    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL 审中-公开
    形成复合材料电路板结构的方法

    公开(公告)号：US20100266752A1

    公开(公告)日：2010-10-21

    申请号：US12763224

    申请日：2010-04-20

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    IPC: H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/036 ,  H05K1/0373 ,  H05K3/181 ,  H05K3/184 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/0257 ,  H05K2203/0264 ,  H05K2203/107 ,  H05K2203/308

    Abstract: A method for forming a circuit board structure of composite material is disclosed. First, a composite material structure including a substrate and a composite material dielectric layer is provided. The composite material dielectric layer includes a catalyst dielectric layer contacting the substrate and at least one sacrificial layer contacting the catalyst dielectric layer. The sacrificial layer is insoluble in water. Later, the composite material dielectric layer is patterned and simultaneously catalyst particles are activated. Then, a conductive layer is formed on the activated catalyst particles. Afterwards, at least one sacrificial layer is removed.

    Abstract translation: 公开了一种形成复合材料的电路板结构的方法。 首先，提供包括基板和复合材料介电层的复合材料结构。 复合材料介电层包括与基底接触的催化剂介电层和与催化剂介电层接触的至少一个牺牲层。 牺牲层不溶于水。 之后，复合材料介电层被图案化，同时催化剂颗粒被激活。 然后，在活化的催化剂颗粒上形成导电层。 之后，去除至少一个牺牲层。

    Substrates for Electronic Circuitry Type Applications
    170.
    发明申请
    Substrates for Electronic Circuitry Type Applications 审中-公开
    电子电路类型应用基板

    公开(公告)号：US20100263919A1

    公开(公告)日：2010-10-21

    申请号：US12086296

    申请日：2006-12-28

    Applicant: Yueh-Ling Lee ,  Meredith L. Dunbar ,  Xin Shane Fang ,  Carl Wang

    Inventor： Yueh-Ling Lee ,  Meredith L. Dunbar ,  Xin Shane Fang ,  Carl Wang

    IPC: H05K1/09 ,  H05K1/00

    CPC classification number: H05K3/185 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1641 ,  C23C18/165 ,  C25D5/02 ,  C25D5/54 ,  H05K1/0373 ,  H05K3/0032 ,  H05K2201/0236

    Abstract: An electronic type substrate having 40 to 97 weight-percent polymer and 3 to 60 weight-percent auto-catalytic crystalline filler. An interconnect or a conductor trace is created in the substrate by: i. drilling or ablating with a high energy electromagnetic source, such as a laser, thereby selectively activating the multi cation crystal filler along the surface created by the drilling or ablating step; and ii. metalizing by electroless and/or electrolytic plating into the drilled or ablated portion of the substrate, where the metal layer is formed in a contacting relationship with the activated multi cation crystal filler at the interconnect boundary without a need for a separate metallization seed layer or pre-dip.

    Abstract translation: 具有40至97重量％聚合物和3至60重量％自催化结晶填料的电子型基材。 通过以下方式在衬底中形成互连或导体迹线：i。 用诸如激光器的高能电磁源进行钻孔或烧蚀，从而沿着由钻孔或烧蚀步骤产生的表面选择性地激活多阳离子晶体填料; 和ii。 通过无电镀和/或电解电镀金属化到衬底的钻孔或烧蚀部分中，其中金属层在互连边界处与活化的多阳离子晶体填料形成接触关系，而不需要单独的金属化种子层或预先 -蘸。

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