公开(公告)号：US20060038264A1

公开(公告)日：2006-02-23

申请号：US11205331

申请日：2005-08-17

Applicant: Toshio Ishimoto

Inventor： Toshio Ishimoto

IPC: H01L23/495

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/3442 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: To provide a printed circuit board in which two wiring patterns having a width of 0.15 mm, which are to be passed through the area of the printed circuit board for mounting a 1608-size chip component, are formed by printing, thereby increasing the circuit packaging density, reducing the production cost and suppressing the yield reduction. In a range in which the distance between two lands 12 to which a surface-mount chip component is electrically connected (the distance between points 17a and 17b) allows formation of two wiring patterns having a line width of 0.25 mm (the distance is equal to or more than 1.25 mm), wiring patterns 15 and 16 having a line width of 0.25 mm are formed. In this way, parts of the wiring patterns having a line width of 0.15 mm (narrow parts 15a and 16a) are minimized, and thus, the reduction in production yield is suppressed.

Abstract translation: 为了提供一种印刷电路板，其中通过印刷形成要穿过用于安装1608尺寸芯片部件的印刷电路板的区域的宽度为0.15mm的两个布线图案，从而增加电路封装 密度，降低生产成本，抑制产量下降。 在表面安装芯片部件电连接的两个焊盘12之间的距离（点17a和17b之间的距离）的范围内，允许形成线宽为0.25mm的两个布线图案（距离为 等于或大于1.25mm），形成线宽为0.25mm的布线图案15和16。 以这种方式，使线宽度为0.15mm的布线图案的部分（窄部分15A和16a）最小化，从而抑制了产量的降低。

公开(公告)号：US20050218502A1

公开(公告)日：2005-10-06

申请号：US11090029

申请日：2005-03-28

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Mitsutoshi Higashi ,  Toshio Gomyo ,  Yukiharu Takeuchi

IPC: H05K3/46 ,  H01L21/4763 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L25/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611

Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Abstract translation: 在电容器安装的布线板中，以所需形状图案化的多个布线层被叠置在其间插入绝缘层，并且通过形成为在厚度方向上刺穿绝缘层的导体彼此连接。 去耦电容器电连接到用作布线层附近的电源线或接地线的布线层，并且安装成使得当电流通过电容器时，电流的方向被反转到 流过相关布线层的电流。

公开(公告)号：US06849944B2

公开(公告)日：2005-02-01

申请号：US10449353

申请日：2003-05-30

Applicant: Masood Murtuza ,  Muthiah Venkateswaran ,  Satyendra S. Chauhan

Inventor： Masood Murtuza ,  Muthiah Venkateswaran ,  Satyendra S. Chauhan

IPC: H01L21/60 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L23/49838 ,  H01L24/81 ,  H01L2224/10165 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2203/0182 ,  Y02P70/613

Abstract: In one embodiment, an integrated circuit package includes a die associated with an integrated circuit and a die pad. The die has a bottom surface, and the pad has a top surface opposite the bottom surface of the die. Two or more bump pad traces are each coupled to the top surface of the pad, and one or more other traces are each coupled to the top surface of the pad in a corresponding inter-bump pad region between adjacent bump pad traces. A number of solder bumps each couple the die to the pad at a corresponding bump pad trace to provide electrical connectivity between circuitry associated with the die and circuitry associated with the die pad. Each inter-bump pad region is free from any solder mask material deposited to control collapse of the die towards the pad during a reflow process for bonding the die to the pad using the bumps, a supporting structure that contacts the die during the reflow process having been used instead.

Abstract translation: 在一个实施例中，集成电路封装包括与集成电路和管芯焊盘相关的管芯。 模具具有底表面，并且垫具有与模具的底表面相对的顶表面。 两个或更多个凸块焊盘迹线各自耦合到焊盘的顶表面，并且一个或多个其它迹线各自在相邻焊盘迹线之间的对应的凸块间焊盘区域中耦合到焊盘的顶表面。 多个焊料凸块每个在相应的凸块焊盘迹线上将焊盘耦合到焊盘，以提供与管芯相关联的电路与与管芯焊盘相关联的电路之间的电连接。 每个凸块间焊盘区域没有任何沉积的焊料掩模材料，以在回流过程期间控制裸片朝向衬垫的塌陷，用于使用凸块将裸片焊接到衬垫上，在回流过程中与裸片接触的支撑结构具有 被改为使用

公开(公告)号：US06835597B2

公开(公告)日：2004-12-28

申请号：US10603812

申请日：2003-06-26

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2144

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/10318 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract translation: 一种半导体封装，其具有包括形成在绝缘基板或绝缘层上的互连图案和焊盘的互连层，覆盖所述焊盘部分以外的所述互连层的保护层和绝缘基板或绝缘层，以及外部连接端子 与从保护层暴露的焊盘接合，外部连接端子被接合到的焊盘由多个焊盘段组成，足够的空间被打开以通过焊盘段之间的互连，并且焊盘段至少包括 连接到互连的一个焊盘段和未连接到互连的其它焊盘段。

公开(公告)号：US20040095725A1

公开(公告)日：2004-05-20

申请号：US10664933

申请日：2003-09-22

Applicant: Fujitsu limited

Inventor： Atsuko Tanaka ,  Masuo Ohnishi

IPC: H05K007/20

CPC classification number: H05K1/0272 ,  G06F1/203 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K2201/064 ,  H05K2201/09072 ,  H05K2201/09772 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A fan housing of a fan unit includes a housing wall standing from the surface of a printed circuit board. The printed circuit board serves to establish the fan housing in cooperation with the housing wall. The fan housing further includes a ceiling wall connected to the housing wall. The ceiling wall extends along a datum plane parallel to the surface of the printed circuit board. A high speed airflow can be generated within the fan housing. The airflow promotes the heat radiation from the printed circuit board. An electrically conductive wiring pattern extending over the surface of the printed circuit board may further promote the heat radiation from the printed circuit board.

Abstract translation: 风扇单元的风扇壳体包括从印刷电路板的表面竖立的壳体壁。 印刷电路板用于与壳体壁一起建立风扇壳体。 风扇壳体还包括连接到壳体壁的顶壁。 顶壁沿平行于印刷电路板表面的基准平面延伸。 风扇外壳内可能产生高速气流。 气流促进印刷电路板的热辐射。 在印刷电路板的表面上延伸的导电布线图形可以进一步促进来自印刷电路板的热辐射。

公开(公告)号：US20030123234A1

公开(公告)日：2003-07-03

申请号：US10233465

申请日：2002-09-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Akihiko Happoya

IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC classification number: H05K3/0094 ,  H05K1/111 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/10636 ,  H05K2203/1394 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed wiring board includes a substrate having a packaging surface and at least one pad mounted on the packaging surface. The pad has an area to solder a circuit component. At least one connection part is placed in the area of the pad. The connection part is electrically insulated from the pad and connected to a circuit electrically different from the pad.

Abstract translation: 印刷电路板包括具有封装表面的基板和安装在封装表面上的至少一个焊盘。 焊盘具有焊接电路部件的区域。 至少一个连接部件被放置在垫的区域中。 连接部分与焊盘电绝缘并连接到与焊盘电气不同的电路。

公开(公告)号：US20030122254A1

公开(公告)日：2003-07-03

申请号：US10103386

申请日：2002-03-21

Inventor： Kevin P. Lyne

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/49816 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Abstract translation: 本发明提供一种用于将一个或多个无源部件构建成芯片级封装的方法和装置。 该方法包括以下步骤：选择具有芯片尺寸封装的封装球距的倍数的端子间距的无源元件，并将所选择的被动元件端子安装到封装的球位。 本发明的优选实施方案使用单一金属层聚酰胺胶带作为包装的基材。 公开了本发明的另外的优选实施例，其中包装球间距的端子间距倍数是一个或两个。 还公开了对应于所公开的方法的设备。

公开(公告)号：US06486412B2

公开(公告)日：2002-11-26

申请号：US09951341

申请日：2001-09-13

Applicant: Hiroki Kato

Inventor： Hiroki Kato

IPC: H05K116

CPC classification number: G02F1/13452 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/323 ,  H05K3/361 ,  H05K7/06 ,  H05K2201/09772 ,  H05K2201/10136 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2224/0401

Abstract: In a wiring board having a mounting region on which an integrated circuit having a plurality of terminals is mounted, and having a plurality of substrate-side wiring lines to be connected to the integrated circuit formed thereon, a conductor pattern is formed to extend in a substantially radial form from a prescribed point in the mounting region to reach two or more of the substrate-side wiring lines to be grounded.

Abstract translation: 在具有安装有多个端子的集成电路的安装区域的布线板中，并且具有与形成在其上的集成电路连接的多个基板侧布线，形成导体图案以在 从安装区域中的规定点起基本上径向地形成两个或更多个待接地的基板侧布线。

公开(公告)号：US20020151200A1

公开(公告)日：2002-10-17

申请号：US10030866

申请日：2002-05-16

Inventor： Edwin Fauser ,  Herman Roozenbeek ,  Wolfgang Schilling ,  Hans Seitel ,  Thomas Wizemann ,  Reinhard Pfendtner ,  Werner Butschkau ,  Wolfgang Hiller ,  Stefan Josten

IPC: H01R013/53

CPC classification number: H05K9/0066 ,  H01T4/08 ,  H05K1/026 ,  H05K1/0272 ,  H05K3/305 ,  H05K3/3442 ,  H05K2201/09772 ,  H05K2201/10295 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The proposal relates to a device for protecting an electrical and/or electronic component, arranged on a carrier substrate, from electrostatic discharges, an overvoltage occurring in the case of discharge at a carrier-substrate contact element connected to the component being diverted to a ground connection, bypassing the component. It is proposed that the protective device include a first electroconductive structure conductively connected to the jeopardized contact element, and a second electroconductive structure arranged adjacent to the first structure on the carrier substrate and conductively connected to the ground connection. Mutually facing sections of the electroconductive structures are set apart spatially from one another by a defined gap in such a way that an overvoltage transmitted to the contact element is transferred by a spark discharge in the gap from the section of the first electroconductive structure to the section of the second electroconductive structure, and is diverted to the ground connection.

Abstract translation: 该提案涉及一种用于保护布置在载体基板上的电气和/或电子部件免受静电放电的装置，在连接到部件的载体 - 基板接触元件被转移到地面处的放电的情况下发生的过电压 连接，绕过组件。 提出了保护装置包括导电连接到危险接触元件的第一导电结构和在载体基板上邻近第一结构设置并导电连接到接地连接的第二导电结构。 导电结构的相互面对的部分通过限定的间隙在空间上彼此分开设置，使得传递到接触元件的过电压通过间隙中的火花放电从第一导电结构的部分转移到部分 的第二导电结构，并被转移到接地连接。

公开(公告)号：US20020019155A1

公开(公告)日：2002-02-14

申请号：US09911428

申请日：2001-07-25

Inventor： Takanori Unou ,  Hiroyuki Kawata ,  Kimio Kobayashi

IPC: H01R004/66

CPC classification number: H05K1/0231 ,  H01L2924/0002 ,  H05K1/111 ,  H05K2201/094 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10522 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: Plural pins are arranged on a printed circuit board to form a generally square shape and are electrically connected to terminals of a QFP-IC. In the pins, a pin disposed at a corner portion of the generally square shape is used as a GND terminal, and a pin adjoining the GND terminal is used as a source terminal. A conductive region is provided to extend radially from the corner portion, and is electrically connected to the ground terminal. Further, another conductive region is provided in the generally square shape and is electrically connected to the radial conductive region.

Abstract translation: 多个引脚布置在印刷电路板上以形成大致正方形形状并且电连接到QFP-IC的端子。 在引脚中，将设置在大致正方形的角部的引脚用作GND端子，并且使用与GND端子相邻的引脚作为源极端子。 导电区域设置成从角部径向延伸，并且电连接到接地端子。 此外，另一个导电区域设置成大致正方形形状并且电连接到径向导电区域。