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    Host transparent storage controller failover/failback of SCSI targets and associated units
    171.
    发明授权
    Host transparent storage controller failover/failback of SCSI targets and associated units 失效
    主机透明存储控制器故障切换/故障恢复SCSI目标和关联单元

    公开(公告)号：US5790775A

    公开(公告)日：1998-08-04

    申请号：US546804

    申请日：1995-10-23

    Applicant: Randal S. Marks ,  Randy L. Roberson ,  Diana Shen ,  Stephen J. Sicola

    Inventor： Randal S. Marks ,  Randy L. Roberson ,  Diana Shen ,  Stephen J. Sicola

    IPC: G06F11/20

    CPC classification number: G06F11/1658 ,  G06F11/2092 ,  G06F2201/85

    Abstract: Provided herein is a method and apparatus for host transparent storage controller failover and failback. A controller is capable of assuming the identity of a failed controller while continuing to respond to its own SCSI ID or IDs in such a way that all SCSI IDs and associated units (LUNS) of the failed controller are effectively taken over by the surviving controller. This "failover" behavior is transparent to any attached host computers and is treated by such attached hosts as a powerfail condition. The symmetric operation of returning the targets (IDs) and units (LUNs) to the previously failing controller ("failback") is likewise transparent.

    Abstract translation: 本文提供了一种用于主机透明存储控制器故障切换和故障恢复的方法和装置。 控制器能够以继续响应其自己的SCSI ID或ID的方式假定故障控制器的身份，使得故障控制器的所有SCSI ID和相关联的单元（LUNS）被有效控制器有效地接管。 这种“故障切换”行为对任何连接的主机都是透明的，并被这样连接的主机视为电源条件。 将目标（ID）和单位（LUN）返回到先前故障的控制器（“故障恢复”）的对称操作同样是透明的。

    Dual bus architecture for a storage device
    172.
    发明授权
    Dual bus architecture for a storage device 失效
    用于存储设备的双总线架构

    公开(公告)号：US5748871A

    公开(公告)日：1998-05-05

    申请号：US514479

    申请日：1995-08-11

    Applicant: Keith B. DuLac ,  Grover G. Phillips

    Inventor： Keith B. DuLac ,  Grover G. Phillips

    IPC: G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F13/00 ,  G11B20/10 ,  G11B31/00 ,  H04N5/765 ,  H04N7/173 ,  G06F11/00

    CPC classification number: G06F11/201 ,  G06F11/1076 ,  H04N7/17336 ,  G06F2201/85 ,  G06F2211/1014

    Abstract: An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter. A second processor circuitry is for transferring data using a second path through the second output to the second buffer storage through the error correction module and from the second buffer storage to the second network adapter, wherein the second processor circuitry is responsive to an error in the storage module.

    Abstract translation: 一种装置包括第一总线，第二总线和具有第一和第二输出的存储模块，其中第一输出端连接到第一总线，第二输出端连接到第二总线。 第一缓冲存储器和第二缓冲存储器，其中第一缓冲存储器连接到第一总线，第二缓冲存储器连接到第二总线。 第二缓冲存储器包括纠错模块。 第一和第二网络适配器分别连接到第一和第二总线。 第一网络适配器还包括到第一缓冲器的连接。 该装置中的处理器包括第一处理器电路，用于使用通过存储模块中的第一输出的第一路径将数据传送到第一缓冲存储器，以及从第一缓冲存储器传送到第一网络适配器。 第二处理器电路用于使用通过第二输出的第二路径将数据传送到第二缓冲存储器，通过纠错模块以及从第二缓冲存储器传送到第二网络适配器，其中第二处理器电路响应于 存储模块

    Real time fault tolerant transaction processing system
    175.
    发明授权
    Real time fault tolerant transaction processing system 失效
    实时容错事务处理系统

    公开(公告)号：US5084816A

    公开(公告)日：1992-01-28

    申请号：US453042

    申请日：1989-12-12

    Applicant: John O. Boese ,  Patrick J. Donnelly ,  Warren S. Gifford ,  Gabriel G. Schlanger

    Inventor： John O. Boese ,  Patrick J. Donnelly ,  Warren S. Gifford ,  Gabriel G. Schlanger

    IPC: G06F11/00 ,  H04Q3/00

    CPC classification number: G06F11/2007 ,  B82Y15/00 ,  G06F11/2005 ,  G06F11/2035 ,  G06F11/2046 ,  H04Q3/0016 ,  G06F11/201 ,  G06F11/2089 ,  G06F2201/85 ,  H04Q2213/13141 ,  H04Q2213/13167 ,  H04Q2213/13176

    Abstract: A real time fault tolerant transaction processing system, particularly one suited for use in a service control point (SCP), is described. Specifically, the system utilizes a communication protocol, such as signalling system 7, that adaptively distributes message packets on an equal basis over multiple physical links that connect two points, such as an SCP and a signalling transfer point (STP), and non-fault tolerant front end and back end processors that are connected to each physical link for processing packets appearing on that link and providing corresponding responses thereto. All the front and back end processors are loosely coupled together for purposes of processor synchronization and re-assignment. Through this system, all the physical links simultaneously carry an equal number of packets which are, in turn, processed by all the processors connected thereto. In the event any physical link or either a front or back end processor connected thereto fails, then that link is declared to be out of service. Consequently, the protocol merely re-assigns all subsequently occurring packets to the other links until such time as the fault is cleared. As the result of link re-assignment, there is advantageously no need to connect a fault tolerant processor to each physical link. This, in turn, substantially and advantageously reduces the complexity and cost of the fault tolerant transaction processing system.

    Abstract translation: 描述了一种特别适用于服务控制点（SCP）的实时容错事务处理系统。 具体地说，该系统利用诸如信令系统7之类的通信协议，其通过连接诸如SCP和信令传送点（STP）两个点的多个物理链路在相等的基础上自适应地分发消息分组，以及非故障 连接到每个物理链路的前端和后端处理器，用于处理出现在该链路上的分组并提供相应的响应。 所有前端和后端处理器松散地耦合在一起，用于处理器同步和重新分配。 通过该系统，所有物理链路同时携带相等数量的分组，这些分组又由与其连接的所有处理器进行处理。 如果任何物理链路或与其连接的前端或后端处理器发生故障，则该链路被声明为停止服务。 因此，该协议仅将所有随后发生的分组重新分配给其他链路，直到故障被清除为止。 作为链路重新分配的结果，有利地不需要将容错处理器连接到每个物理链路。 这反过来又实质上有利地降低了容错事务处理系统的复杂性和成本。

    Fault tolerant least recently used algorithm logic
    176.
    发明授权
    Fault tolerant least recently used algorithm logic 失效
    容错最小最近使用的算法逻辑

    公开(公告)号：US3958228A

    公开(公告)日：1976-05-18

    申请号：US560421

    申请日：1975-03-20

    Applicant: Daniel J. Coombes ,  Benedicto U. Messina

    Inventor： Daniel J. Coombes ,  Benedicto U. Messina

    IPC: G06F11/20 ,  G06F11/00 ,  G06F12/12 ,  G06F7/00

    CPC classification number: G06F11/1666 ,  G06F12/126 ,  G06F11/20 ,  G06F2201/85

    Abstract: Binary logic is added to the binary logic normally utilized for the purpose of generating and decoding binary code combinations which reflect the order of use of a number of units, utilized in sequence, to thereby indicate the unit least recently used (LRU). Disclosed is the utilization of six binary bits which are updated in accordance with a sequence of use of four units to thereby indicate the least recently used one of the four units. In accordance with known LRU techniques, there are 24 valid binary bit combinations that reflect the sequence of use of the four units. The provision of 6 binary bits in the LRU code are capable of assuming 64 different permutations, therefore 40 combinations of binary bits are considered invalid when utilizing the LRU code. The present invention utilizes certain of the invalid binary bit combinations to identify units that have been removed from further use because of a fault condition, and which code continues to identify the sequence of use of those units which have not been eliminated from further use. The code chosen to identify a faulty unit and the sequence of use of the remaining units is fault tolerant in that additional errors in the coding mechanism can be tolerated, and ignored, while maintaining the ability to identify faulty units and sequence of use of the remaining units.

    Computer communications system
    177.
    发明授权
    Computer communications system 失效
    计算机通信系统

    公开(公告)号：US3623014A

    公开(公告)日：1971-11-23

    申请号：US3623014D

    申请日：1969-08-25

    Applicant: CONTROL DATA CORP

    Inventor： DOELZ MELVIN L ,  MARTIN ROBERT F ,  MORIOKA FRED K

    IPC: G06F11/00 ,  G06F15/167 ,  G06F15/16

    CPC classification number: G06F11/2035 ,  G06F11/076 ,  G06F11/2087 ,  G06F11/2094 ,  G06F15/167 ,  G06F2201/85

    Abstract: A computer controlled, data communications system is provided for transmitting data between a plurality of external devices. The system comprises up to eight, general purpose, digital computers, each with an associated disc-file storage system. The computers and the disc-file storage units are organized such that communication between the computers is made via the disc-file storage associated with each computer, not directly between the computers themselves. Each group of external devices is coupled to a primary and secondary computer such that upon the failure of the primary computer, the secondary computer will procss the data for its primary group of devices as well as for those external devices for which it is the secondary computer. Each disc-file storage unit is the primary storage for one computer and the copy storage for one additional computer. Upon the failure of a primary disc-file storage unit, a computer can operate with the copy storage unit.

    CONTROL DEVICE AND METHOD FOR OPERATING CONTROL DEVICE
    178.
    发明公开
    CONTROL DEVICE AND METHOD FOR OPERATING CONTROL DEVICE 审中-公开

    公开(公告)号：US20240338285A1

    公开(公告)日：2024-10-10

    申请号：US18241492

    申请日：2023-09-01

    Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

    Inventor： Michitomo YAMAGUCHI ,  Satoshi KAMIYA ,  Hiroshi ICHIKAWA

    IPC: G06F11/20 ,  G06F11/16

    CPC classification number: G06F11/2028 ,  G06F11/1679 ,  G06F2201/85

    Abstract: A control device according to an embodiment includes a first region including a CPU and a sequence signal generation circuit; and a second region including an abnormality detection circuit, a sequence signal detection circuit, a first register storing multiple methods of recovery from occurrence of abnormality, and a second register for use to select one method of recovery from the multiple methods of recovery, the second region being higher in reliability than the first region. The sequence signal generation circuit converts a first signal that specifies the one method of recovery into a sequence signal containing a second signal, which is a digital signal of a predetermined pattern, and the sequence signal detection circuit changes a set value of the second register upon receiving the second signal.

    DATA MANAGEMENT APPARATUS AND DR COST CALCULATION SUPPORT METHOD
    179.
    发明公开
    DATA MANAGEMENT APPARATUS AND DR COST CALCULATION SUPPORT METHOD 审中-公开

    公开(公告)号：US20240311261A1

    公开(公告)日：2024-09-19

    申请号：US18459633

    申请日：2023-09-01

    Applicant: Hitachi, Ltd.

    Inventor： Noriko ICHIKAWA ,  Jun Nakajima ,  Koichi Murayama

    IPC: G06F11/20

    CPC classification number: G06F11/2025 ,  G06F2201/85

    Abstract: Upon acquiring target business specifying information for specifying a target business, disaster recovery (DR) operation phase determination processing of calculating an operation phase is executed based on copy configuration information for managing a pair configuration of a target business use volume and a copy volume and a copy status table for managing a copy status in the target business use volume and the copy volume, a disaster pattern corresponding to a disaster situation of a volume of a disaster target having been damaged is calculated in accordance with an operation phase calculated by the DR operation phase determination unit, and a cloud use fee is calculated for each disaster pattern from a failure occurrence to completion of system recovery of a use site where a use volume is created.

    Early database transaction visibility
    180.
    发明授权
    Early database transaction visibility 有权

    公开(公告)号：US12086041B2

    公开(公告)日：2024-09-10

    申请号：US18045260

    申请日：2022-10-10

    Applicant: Salesforce, Inc.

    Inventor： Kaushal Mittal ,  James E. Mace ,  Jun Chen ,  Shao-Yuan Ho

    IPC: G06F16/24 ,  G06F11/20 ,  G06F16/2455

    CPC classification number: G06F11/2092 ,  G06F16/2455 ,  G06F2201/85

    Abstract: The disclosed techniques reduce a responsiveness time for a secondary node state of a database in switching from a second computing node to replace a first computing node acting in a primary node state, with both computing nodes performing the same database queries. The second node receives information regarding queries performed by the first node while in the primary state. In some embodiments, the second node retrieves, from a transaction log, log records detailing operations performed for database transactions. In some embodiments, the second node inserts, based on the log records, data records of the transactions into an in-memory cache of the second node that stores chains of database records from different transactions. Upon receiving sufficient information to switch to the primary state, the second node changes a mode of operation during failover making a committed transaction available for reads by subsequent database queries prior to record reordering.

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