公开(公告)号：US07449364B2

公开(公告)日：2008-11-11

申请号：US11460859

申请日：2006-07-28

Applicant: Kevin P. Lyne

Inventor： Kevin P. Lyne

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40

CPC classification number: H01L23/49816 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/113 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09772 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal pitch that is a multiple of the package ball pitch of a chip scale package and mounting the selected passive component terminals to ball sites of the package. A preferred embodiment of the invention uses a single metal layer polyamide tape as the substrate of the package. Additional preferred embodiments of the invention are disclosed in which the terminal pitch multiple of the package ball pitch is one or two. Devices corresponding to the disclosed methods are also disclosed.

Abstract translation: 本发明提供一种用于将一个或多个无源部件构建成芯片级封装的方法和装置。 该方法包括以下步骤：选择具有芯片尺寸封装的封装球距的倍数的端子间距的无源元件，并将所选择的被动元件端子安装到封装的球位。 本发明的优选实施方案使用单一金属层聚酰胺胶带作为包装的基材。 公开了本发明的另外的优选实施例，其中包装球间距的端子间距倍数是一个或两个。 还公开了对应于所公开的方法的设备。

公开(公告)号：US07367116B2

公开(公告)日：2008-05-06

申请号：US10891190

申请日：2004-07-15

Applicant: Toyokazu Yoshino ,  Kouji Nakashima

Inventor： Toyokazu Yoshino ,  Kouji Nakashima

IPC: H05K3/36 ,  H05K3/00 ,  H01R9/00

CPC classification number: H05K3/4038 ,  H05K3/4046 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0215 ,  H05K2201/0305 ,  H05K2201/096 ,  H05K2201/10234 ,  Y10T29/49126 ,  Y10T29/49149 ,  Y10T29/49153

Abstract: To provide an interlayer-connected, multi-layer flexible printed circuit board having high bonding reliability and most suitable for micropatterning the circuit layers in the device; and to provide a high-productivity method for fabricating the device.A multi-layer flexible printed circuit board, wherein a conductor is filled in the through-holes formed in the insulating layer in the direction of the thickness thereof so as to electrically interconnect the circuit layers formed on both faces of the insulating layer, and wherein the conductor contains inside it, a copper-core solder ball having a copper ball as a core thereof.

Abstract translation: 提供层间连接的多层柔性印刷电路板，其具有高结合可靠性并且最适合于将装置中的电路层微图案化; 并且提供用于制造该器件的高生产率方法。 一种多层柔性印刷电路板，其中导电体在其厚度方向上填充在形成在绝缘层中的通孔中，以使形成在绝缘层的两个面上的电路层电连接，并且其中 导体内部含有以铜球为核心的铜芯焊球。

公开(公告)号：US07329943B2

公开(公告)日：2008-02-12

申请号：US11416824

申请日：2006-05-03

Applicant: Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

Inventor： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC: H01L29/40

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Abstract translation: 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US20070246511A1

公开(公告)日：2007-10-25

申请号：US11409244

申请日：2006-04-21

Applicant: Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

Inventor： Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

IPC: A47J36/02

CPC classification number: H05K3/3484 ,  B23K3/0607 ,  B23K2101/42 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09472 ,  H05K2203/0126 ,  H05K2203/043 ,  H05K2203/0568

Abstract: A system, method, and apparatus of providing conductive bonding material into a plurality of cavities in a circuit supporting substrate is disclosed. The method comprises placing a fill head in substantial contact with a circuit supporting substrate. The circuit supporting substrate includes at least one cavity. A linear motion or a rotational motion is provided to at least one of the circuit supporting substrate and the fill head while the fill head is in substantial contact with the circuit supporting substrate. Conductive bonding material is forced out of the fill head toward the circuit supporting substrate. The conductive bonding material is provided into the at least one cavity contemporaneous with the at least one cavity being in proximity to the fill head.

Abstract translation: 公开了一种在电路支撑衬底中的多个空腔中提供导电接合材料的系统，方法和装置。 该方法包括将填充头放置成与电路支撑衬底基本接触。 电路支撑衬底包括至少一个空腔。 当填充头与电路支撑衬底基本接触时，向电路支撑衬底和填充头中的至少一个提供直线运动或旋转运动。 导电接合材料被迫从填充头朝向电路支撑基板排出。 所述导电接合材料被提供到与所述至少一个空腔同时的至少一个空腔中，所述至少一个空腔在所述填充头附近。

公开(公告)号：US20070216019A1

公开(公告)日：2007-09-20

申请号：US11616299

申请日：2006-12-27

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/12

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/3473 ,  H05K3/4038 ,  H05K3/462 ,  H05K2201/0305 ,  H05K2201/09572 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A laminated IC packaging substrate includes an intermediate connecting layer having a plurality of through holes. Each of the through holes is filled with solder material protruding from a top surface and/or a bottom surface of the intermediate connecting layer. A first circuit board having thereon a first wiring pattern is adhered to the top surface of the intermediate connecting layer using a first adhesive layer. A second circuit board having thereon a second wiring pattern is adhered to the bottom surface of the intermediate connecting layer using a second adhesive layer.

Abstract translation: 层压IC封装基板包括具有多个通孔的中间连接层。 每个通孔都填充有从中间连接层的顶表面和/或底表面突出的焊料材料。 其上具有第一布线图案的第一电路板使用第一粘合剂层粘合到中间连接层的顶表面。 具有第二布线图案的第二电路板使用第二粘合剂层粘附到中间连接层的底表面。

公开(公告)号：US07232754B2

公开(公告)日：2007-06-19

申请号：US10879838

申请日：2004-06-29

Applicant: Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

Inventor： Kyle K. Kirby ,  Salman Akram ,  David R. Hembree ,  Sidney B. Rigg ,  Warren M. Farnworth ,  William M. Hiatt

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/09827 ,  H05K2203/072 ,  H05K2203/1147 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.

Abstract translation: 本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。 在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。 衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。 该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。 该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。 该方法然后包括用导电材料填充通道。

公开(公告)号：US07211892B2

公开(公告)日：2007-05-01

申请号：US11146044

申请日：2005-06-07

Applicant: Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

Inventor： Shiro Yamashita ,  Yoichi Abe ,  Kenichi Yamamoto ,  Ryosuke Kimoto ,  Hiroshi Kawakubo

IPC: H01L29/40

CPC classification number: H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3463 ,  H05K2201/0305 ,  H05K2203/0361 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed on the metal layer, in the present invention, gold (Au) is contained in the metal layer, the metal bump is made of solder mainly made of Sn and designed to have an average height H of 100 μm or less per unit area in the electrode pad, and the concentration of Au of the metal layer dissolved in the solder is set to 1.3×10−3 (Vol %) or less. More preferably, the metal bump contains palladium (Pd), and the solder coating for forming the metal bump on the electrode pad is performed by using the dipping and the paste printing in combination.

Abstract translation: 为了抑制由于在具有电极焊盘的半导体器件中电极焊盘的连接界面强度的劣化及其翘曲导致的连接故障，形成在电极焊盘上的金属层和形成在金属上的金属凸块 在本发明中，在金属层中含有金（Au），金属凸块由主要由Sn制成的焊料制成，并且设计成在电极焊盘中的每单位面积的平均高度H为100mum以下， 并且溶解在焊料中的金属层的Au浓度设定为1.3×10 -3（Vol％）以下。 更优选地，金属凸块包含钯（Pd），并且通过组合使用浸渍和糊印来进行用于在电极焊盘上形成金属凸块的焊料涂层。

公开(公告)号：US07191515B2

公开(公告)日：2007-03-20

申请号：US10628594

申请日：2003-07-28

Applicant: Robert C. Sundahl ,  Kenneth Wong

Inventor： Robert C. Sundahl ,  Kenneth Wong

IPC: H05K3/36

CPC classification number: H05K3/4629 ,  H01L27/3281 ,  H01L2224/13 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K3/28 ,  H05K3/321 ,  H05K3/4015 ,  H05K3/4038 ,  H05K3/4614 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0367 ,  H05K2201/2036 ,  H05K2203/1327 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49172 ,  H01L2924/00

Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).

Abstract translation: 电气组件（200，图2）由两个互连的电路板（202,204）形成。 导电间隔物（240）和导电材料（260）放置在电路板上的互补焊盘（218,232）之间。 导电间隔物由在连接电路板的过程中保持其机械完整性的材料形成。 导电材料是用于机械地连接电路板的焊料或导电粘合剂。 此外，将绝缘材料（270）插入到电路板之间的界面区域（250）中。 绝缘材料在电路板之间提供额外的机械连接。 在一个实施例中，一个电路板（202）包括保持有机发光二极管（OLED）阵列的玻璃面板，另一个电路板（204）是陶瓷电路板。 互连电路板组件（200）一起形成平板显示器（1102，图11）的一部分。

公开(公告)号：US07188412B2

公开(公告)日：2007-03-13

申请号：US10662368

申请日：2003-09-16

Applicant: Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

Inventor： Yoshitarou Yazaki ,  Tomohiro Yokochi ,  Koji Kondo ,  Toshikazu Harada ,  Yoshihiko Shiraishi

IPC: H01K3/10

CPC classification number: H05K3/4632 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0272 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0425 ,  H05K2203/1131 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Conductive paste containing tin particles and silver particles is packed in a substantially cylindrical via hole formed in a thermoplastic resin film that interposes between conductor patterns and is hot-pressed from both sides. When the metal particles contained in the conductive paste are sintered to form a unified conductive compound, the volume of the conductive paste shrinks. Synchronously, the resin film around the via-hole protrudes into the via-hole. Therefore, the shape of the side wall on the cross-section of the conductive compound provides an arch shape, and a side wall adjacent to a junction part of the conductive compound, which contacts the conductor pattern, is formed with an inclination. Therefore, it is possible to prevent the stress concentration due to deformation of the board.

Abstract translation: 含有锡颗粒和银颗粒的导电糊料被包装在形成在热塑性树脂膜中的大致圆柱形的通孔中，该热塑性树脂膜介于导体图案之间并且从两侧被热压。 当包含在导电浆料中的金属颗粒被烧结以形成统一的导电化合物时，导电浆料的体积收缩。 同时，通孔周围的树脂膜突出到通孔中。 因此，导电性化合物的横截面上的侧壁的形状形成拱形，并且与导体图案接触的导电性化合物的接合部分相邻的侧壁形成倾斜。 因此，可以防止由于板的变形引起的应力集中。

公开(公告)号：US07156279B2

公开(公告)日：2007-01-02

申请号：US10149031

申请日：2001-10-03

Applicant: Lakhi N. Goenke ,  Charles Frederick Schweitzer ,  Jason Bullock, legal representative ,  Shona Bullock, legal representative ,  Mark D. Miller ,  Jay DeAvis Baker ,  Karen Lee Chiles ,  Achyuta Achari

Inventor： Lawrence Lernel Bullock, deceased

IPC: B23K1/00

CPC classification number: H05K3/3494 ,  B23K1/008 ,  B23K3/085 ,  B23K3/087 ,  B23K2101/40 ,  B23K2101/42 ,  H05K2201/0305 ,  H05K2203/0165 ,  H05K2203/081 ,  H05K2203/111 ,  H05K2203/1121 ,  H05K2203/1581 ,  H05K2203/304

Abstract: A system and method for reflowing solder to interconnect a plurality of electronic components (24) to a substrate (12) is disclosed. The system includes an oven for preheating the substrate (12) and the plurality of electronic components (24) disposed thereon, a supplemental heat source disposed in the oven for providing additional heat energy to reflow the solder (72), a pallet (14 ) for supporting the substrate (12), wherein the pallet (14) has at least one internal cavity (40), and a phase-transition material (42) disposed within the cavity (40) for absorbing heat from the pallet (14).

Abstract translation: 公开了一种用于回流焊料以将多个电子部件（24）互连到基板（12）的系统和方法。 该系统包括用于预热基板（12）和设置在其上的多个电子部件（24）的烘箱，设置在烘箱中的补充热源，用于提供额外的热能以回流焊料（72），托盘（14） 用于支撑所述基底（12），其中所述托盘（14）具有至少一个内部空腔（40）以及设置在所述空腔（40）内用于从所述托盘（14）吸收热量的相变材料（42）。