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    DIMENSION COMPENSATION CONTROL FOR DIRECTLY BONDED STRUCTURES
    11.
    发明公开
    DIMENSION COMPENSATION CONTROL FOR DIRECTLY BONDED STRUCTURES 审中-公开

    公开(公告)号：US20240312953A1

    公开(公告)日：2024-09-19

    申请号：US18671851

    申请日：2024-05-22

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh

    IPC: H01L23/00

    CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/80031 ,  H01L2224/80143 ,  H01L2224/80895 ,  H01L2224/80896

    Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

    Microelectronic assemblies
    15.
    发明授权
    Microelectronic assemblies 有权

    公开(公告)号：US12046482B2

    公开(公告)日：2024-07-23

    申请号：US17937593

    申请日：2022-10-03

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES, INC.

    Inventor： Belgacem Haba

    IPC: H01L21/56 ,  H01L21/768 ,  H01L21/82 ,  H01L23/31 ,  H01L23/528

    CPC classification number: H01L21/565 ,  H01L21/76819 ,  H01L21/76877 ,  H01L21/82 ,  H01L23/3107 ,  H01L23/528 ,  H01L2224/02379

    Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

    METHOD FOR PREPARING A SURFACE FOR DIRECT-BONDING
    16.
    发明公开
    METHOD FOR PREPARING A SURFACE FOR DIRECT-BONDING 审中-公开

    公开(公告)号：US20240234159A9

    公开(公告)日：2024-07-11

    申请号：US18475977

    申请日：2023-09-27

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Jeremy Alfred Theil

    IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L23/00

    CPC classification number: H01L21/31053 ,  H01L21/0217 ,  H01L21/31111 ,  H01L24/83 ,  H01L2224/83031 ,  H01L2224/83896

    Abstract: Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

    SYSTEM AND METHOD FOR USING ACOUSTIC WAVES TO COUNTERACT DEFORMATIONS DURING BONDING
    18.
    发明公开
    SYSTEM AND METHOD FOR USING ACOUSTIC WAVES TO COUNTERACT DEFORMATIONS DURING BONDING 审中-公开

    公开(公告)号：US20240213210A1

    公开(公告)日：2024-06-27

    申请号：US18146265

    申请日：2022-12-23

    Applicant: Adeia Semiconductor Bonding Technologies Inc.

    Inventor： Belgacem Haba ,  Pawel Mrozek

    IPC: H01L23/00

    CPC classification number: H01L24/80 ,  H01L24/74 ,  H01L2224/802 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80908

    Abstract: A method includes moving at least one of a first element and a second element to contact first regions of the first and second elements with one another while second regions of the first and second elements are not in contact with one another. The first regions directly bond to one another to form a bond interface without adhesive. The method further includes directly bonding the second regions of the first and second elements to one another without adhesive by controllably releasing one of the first element and the second element such that the bond interface and a boundary between the bond interface and the second regions not in contact with one another expands radially away from the first regions. The second regions have first vibrations within a bond initiation region bordering the boundary. The method further includes externally applying second vibrations to at least one of the first and second elements during the directly bonding. The second vibrations are in antiphase with the first vibrations in the bond initiation region.

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