公开(公告)号：US20110034014A1

公开(公告)日：2011-02-10

申请号：US12850271

申请日：2010-08-04

Applicant: Christopher R. Hatem ,  Benjamin Colombeau ,  Thirumal Thanigaivelan ,  Kyu-Ha Shim ,  Jay T. Scheuer

Inventor： Christopher R. Hatem ,  Benjamin Colombeau ,  Thirumal Thanigaivelan ,  Kyu-Ha Shim ,  Jay T. Scheuer

IPC: H01L21/265 ,  H01L21/425 ,  H01L21/38

CPC classification number: H01J37/20 ,  H01J37/3171 ,  H01J2237/2001 ,  H01J2237/31701 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/28518 ,  H01L21/823814

Abstract: A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained.

Abstract translation: 公开了将金属或“管道”的横向扩散最小化等不利影响最小化的硅化物施加于基板的方法。 半导体器件的源极和漏极区域的注入在低于0℃的低温下进行。该冷植入物减少了由冲击离子引起的结构损伤。 随后，施加硅化物层，并且由于结构损伤减小，金属扩散和管道进入衬底被减少。 在一些实施方案中，在植入掺杂剂之后但在施加硅化物之前进行非晶化注入。 通过在寒冷的温度下进行这种预硅化物种植体，可获得类似的结果。

公开(公告)号：US20110033998A1

公开(公告)日：2011-02-10

申请号：US12851141

申请日：2010-08-05

Applicant: Christopher R. Hatem ,  Benjamin Colombeau ,  Thirumal Thanigaivelan ,  Kyu-Ha Shim ,  Dennis Rodier

Inventor： Christopher R. Hatem ,  Benjamin Colombeau ,  Thirumal Thanigaivelan ,  Kyu-Ha Shim ,  Dennis Rodier

IPC: H01L21/22

CPC classification number: H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.

Abstract translation: 公开了一种执行口袋或晕轮植入物的改进方法。 通过增加漏电流，降低噪声容限和增加最小栅极电压，由晕轮植入物造成的损伤和缺陷的量会降低半导体器件的性能。 卤素或分组注入在冷温度下进行，这降低了对晶体结构的损害，并改善了晶体的非晶化。 使用冷温度还允许使用较轻的元素用于卤素注入，例如硼或磷。

公开(公告)号：US20100019329A1

公开(公告)日：2010-01-28

申请号：US12220792

申请日：2008-07-28

Applicant: Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

Inventor： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC: H01L27/088 ,  H01L21/66 ,  G06F17/50

CPC classification number: H01L27/088 ,  H01L27/0211

Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Abstract translation: 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US08722431B2

公开(公告)日：2014-05-13

申请号：US13426785

申请日：2012-03-22

Applicant: Nilay Anil Pradhan ,  Stanislav S. Todorov ,  Kurt Decker-Lucke ,  Klaus Petry ,  Benjamin Colombeau ,  Baonian Guo

Inventor： Nilay Anil Pradhan ,  Stanislav S. Todorov ,  Kurt Decker-Lucke ,  Klaus Petry ,  Benjamin Colombeau ,  Baonian Guo

IPC: H01L21/00

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/76243

Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.

Abstract translation: 一种形成FinFET器件的方法。 该方法可以包括提供具有单晶区域的衬底，将衬底加热到​​衬底温度以有效地在离子注入期间动态地去除注入损伤，在将衬底保持在衬底温度的同时将离子注入到衬底中，并且使单晶 以形成单晶翅片。

公开(公告)号：US08293544B2

公开(公告)日：2012-10-23

申请号：US12220792

申请日：2008-07-28

Applicant: Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

Inventor： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC: H01L21/00

CPC classification number: H01L27/088 ,  H01L27/0211

Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Abstract translation: 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US08101528B2

公开(公告)日：2012-01-24

申请号：US12850317

申请日：2010-08-04

Applicant: Christopher R. Hatem ,  Benjamin Colombeau

Inventor： Christopher R. Hatem ,  Benjamin Colombeau

IPC: H01L21/31

CPC classification number: H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/268

Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.

Abstract translation: 公开了一种在最小化成本和制造时间的同时对基板进行处理的方法。 半导体器件的源极和漏极区域的注入在诸如低于273°K的低温下进行。该低温植入物减少了由冲击离子引起的结构损伤。 随后，使用更快形式的退火激活注入的衬底。 通过在低温下进行植入，对衬底的损伤降低，从而允许使用快速退火来激活掺杂剂，同时消除大部分缺陷和损伤。 快速退火比传统的炉退火更便宜，并且可以以更低的成本实现更高的产量。

公开(公告)号：US20110034013A1

公开(公告)日：2011-02-10

申请号：US12850317

申请日：2010-08-04

Applicant: Christopher R. Hatem ,  Benjamin Colombeau

Inventor： Christopher R. Hatem ,  Benjamin Colombeau

IPC: H01L21/265

CPC classification number: H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/268

Abstract: A method of processing to a substrate while minimizing cost and manufacturing time is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at low temperatures, such as below 273° K. This low temperature implant reduces the structural damage caused by the impacting ions. Subsequently, the implanted substrate is activated using faster forms of annealing. By performing the implant at low temperatures, the damage to the substrate is reduced, thereby allowing a fast anneal to be used to activate the dopants, while eliminating the majority of the defects and damage. Fast annealing is less expensive than conventional furnace annealing, and can achieve higher throughput at lower costs.

Abstract translation: 公开了一种在最小化成本和制造时间的同时对基板进行处理的方法。 半导体器件的源极和漏极区域的注入在诸如低于273°K的低温下进行。该低温植入物减少了由冲击离子引起的结构损伤。 随后，使用更快形式的退火激活注入的衬底。 通过在低温下进行植入，对衬底的损伤降低，从而允许使用快速退火来激活掺杂剂，同时消除大部分缺陷和损伤。 快速退火比传统的炉退火更便宜，并且可以以更低的成本实现更高的产量。