公开(公告)号：US20090286373A1

公开(公告)日：2009-11-19

申请号：US12466391

申请日：2009-05-15

Applicant: Dexter Xueming TAN ,  Benjamin COLOMBEAU ,  Clark Kuang Kian ONG ,  Sai Hooi YEONG ,  Chee Mang NG ,  Kin Leong PEY

Inventor： Dexter Xueming TAN ,  Benjamin COLOMBEAU ,  Clark Kuang Kian ONG ,  Sai Hooi YEONG ,  Chee Mang NG ,  Kin Leong PEY

IPC: H01L21/336 ,  H01L21/322

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

Abstract translation: 本发明提供一种制造半导体器件的方法。 该方法包括提供衬底并在衬底上形成栅叠层。 执行在栅极堆叠的相对侧上在衬底内形成空位丰富区域的第一激光处理。 空位丰富区域具有从基板表面的第一深度。 还执行第一种植入物，其在基板的表面的第二深度处形成在栅叠层的相对侧上形成范围缺陷区域的端部，其中第一深度接近第二深度。

公开(公告)号：US08354321B2

公开(公告)日：2013-01-15

申请号：US13277197

申请日：2011-10-19

Applicant: Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

Inventor： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

IPC: H01L21/336 ,  H01L21/76

CPC classification number: H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract translation: 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US20120034745A1

公开(公告)日：2012-02-09

申请号：US13277197

申请日：2011-10-19

Applicant: Benjamin COLOMBEAU ,  Sai Hooi YEONG ,  Francis BENISTANT ,  Bangun INDAJANG ,  Lap CHAN

Inventor： Benjamin COLOMBEAU ,  Sai Hooi YEONG ,  Francis BENISTANT ,  Bangun INDAJANG ,  Lap CHAN

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract translation: 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US08101487B2

公开(公告)日：2012-01-24

申请号：US12466391

申请日：2009-05-15

Applicant: Dexter Xueming Tan ,  Benjamin Colombeau ,  Clark Kuang Kian Ong ,  Sai Hooi Yeong ,  Chee Mang Ng ,  Kin Leong Pey

Inventor： Dexter Xueming Tan ,  Benjamin Colombeau ,  Clark Kuang Kian Ong ,  Sai Hooi Yeong ,  Chee Mang Ng ,  Kin Leong Pey

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is presented. The method includes providing a substrate and forming a gate stack over the substrate. A first laser processing to form vacancy rich regions within the substrate on opposing sides of the gate stack is performed. The vacancy rich regions have a first depth from a surface of the substrate. A first implant causing end of range defect regions to be formed on opposing sides of the gate stack at a second depth from the surface of the substrate is also carried out, wherein the first depth is proximate to the second depth.

Abstract translation: 提出了一种制造半导体器件的方法。 该方法包括提供衬底并在衬底上形成栅叠层。 执行在栅极堆叠的相对侧上在衬底内形成空位丰富区域的第一激光处理。 空位丰富区域具有从基板表面的第一深度。 还执行第一种植入物，其在基板的表面的第二深度处形成在栅堆叠的相对侧上形成范围缺陷区域的端部，其中第一深度接近第二深度。

公开(公告)号：US20130313971A1

公开(公告)日：2013-11-28

申请号：US13477253

申请日：2012-05-22

Applicant: Costel Biloiu ,  Craig R. Chaney ,  Neil J. Bassom ,  Benjamin Colombeau ,  Dennis P. Rodier

Inventor： Costel Biloiu ,  Craig R. Chaney ,  Neil J. Bassom ,  Benjamin Colombeau ,  Dennis P. Rodier

IPC: H01J27/20

CPC classification number: H01J27/20 ,  H01J7/24 ,  H01J37/02 ,  H01J37/08

Abstract: In one embodiment, a method for generating an ion beam having gallium ions includes providing at least a portion of a gallium compound target in a plasma chamber, the gallium compound target comprising gallium and at least one additional element. The method also includes initiating a plasma in the plasma chamber using at least one gaseous species and providing a source of gaseous etchant species to react with the gallium compound target to form a volatile gallium species.

Abstract translation: 在一个实施方案中，用于产生具有镓离子的离子束的方法包括在等离子体室中提供镓化合物靶的至少一部分，所述镓化合物靶包含镓和至少一个附加元素。 该方法还包括使用至少一种气态物质在等离子体室中引发等离子体，并提供气态蚀刻剂物质源以与镓化合物靶反应以形成挥发性镓物质。

公开(公告)号：US20130252349A1

公开(公告)日：2013-09-26

申请号：US13426785

申请日：2012-03-22

Applicant: Nilay Anil Pradhan ,  Stanislav S. Todorov ,  Kurt Decker-Lucke ,  Klaus Petry ,  Benjamin Colombeau ,  Baonian Guo

Inventor： Nilay Anil Pradhan ,  Stanislav S. Todorov ,  Kurt Decker-Lucke ,  Klaus Petry ,  Benjamin Colombeau ,  Baonian Guo

IPC: H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/76243

Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.

Abstract translation: 一种形成FinFET器件的方法。 该方法可以包括提供具有单晶区域的衬底，将衬底加热到​​衬底温度以有效地在离子注入期间动态地去除注入损伤，在将衬底保持在衬底温度的同时将离子注入到衬底中，并且使单晶 以形成单晶翅片。

公开(公告)号：US08053340B2

公开(公告)日：2011-11-08

申请号：US11862213

申请日：2007-09-27

Applicant: Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

Inventor： Benjamin Colombeau ,  Sai Hooi Yeong ,  Francis Benistant ,  Bangun Indajang ,  Lap Chan

IPC: H01L21/425 ,  H01L21/22 ,  H01L21/38

CPC classification number: H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract translation: 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US20090087971A1

公开(公告)日：2009-04-02

申请号：US11862213

申请日：2007-09-27

Applicant: Benjamin COLOMBEAU ,  Sai Hooi YEONG ,  Francis BENISTANT ,  Bangun INDAJANG ,  Lap CHAN

Inventor： Benjamin COLOMBEAU ,  Sai Hooi YEONG ,  Francis BENISTANT ,  Bangun INDAJANG ,  Lap CHAN

IPC: H01L29/94 ,  H01L21/22

CPC classification number: H01L29/78612 ,  H01L29/66537 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling.

Abstract translation: 一种晶体管，其包括设置在与栅极的相对侧相邻的衬底中的晕圈。 晕区具有上部和下部区域。 上部区域是具有多余空位的结晶区域，下部区域是非晶区域。 源极/漏极扩散区域设置在光晕区域中。 源极/漏极扩散区域与上部和下部晕圈重叠。 该架构提供最小的延伸电阻以及最小的横向扩散，以实现更好的CMOS器件缩放。

公开(公告)号：US09396902B2

公开(公告)日：2016-07-19

申请号：US13477253

申请日：2012-05-22

Applicant: Costel Biloiu ,  Craig R. Chaney ,  Neil J. Bassom ,  Benjamin Colombeau ,  Dennis P. Rodier

Inventor： Costel Biloiu ,  Craig R. Chaney ,  Neil J. Bassom ,  Benjamin Colombeau ,  Dennis P. Rodier

IPC: H01J7/24 ,  H01J27/20 ,  H01J37/02 ,  H01J37/08

CPC classification number: H01J27/20 ,  H01J7/24 ,  H01J37/02 ,  H01J37/08

Abstract: In one embodiment, a method for generating an ion beam having gallium ions includes providing at least a portion of a gallium compound target in a plasma chamber, the gallium compound target comprising gallium and at least one additional element. The method also includes initiating a plasma in the plasma chamber using at least one gaseous species and providing a source of gaseous etchant species to react with the gallium compound target to form a volatile gallium species.

Abstract translation: 在一个实施方案中，用于产生具有镓离子的离子束的方法包括在等离子体室中提供镓化合物靶的至少一部分，所述镓化合物靶包含镓和至少一个附加元素。 该方法还包括使用至少一种气态物质在等离子体室中引发等离子体，并提供气态蚀刻剂物质源以与镓化合物靶反应以形成挥发性镓物质。

公开(公告)号：US08012843B2

公开(公告)日：2011-09-06

申请号：US12851141

申请日：2010-08-05

Applicant: Christopher R. Hatem ,  Benjamin Colombeau ,  Thirumal Thanigaivelan ,  Kyu-Ha Shim ,  Dennis Rodier

Inventor： Christopher R. Hatem ,  Benjamin Colombeau ,  Thirumal Thanigaivelan ,  Kyu-Ha Shim ,  Dennis Rodier

IPC: H01L21/331

CPC classification number: H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

Abstract: An improved method of performing pocket or halo implants is disclosed. The amount of damage and defects created by the halo implant degrades the performance of the semiconductor device, by increasing leakage current, decreasing the noise margin and increasing the minimum gate voltage. The halo or packet implant is performed at cold temperature, which decreases the damage caused to the crystalline structure and improves the amorphization of the crystal. The use of cold temperature also allows the use of lighter elements for the halo implant, such as boron or phosphorus.

Abstract translation: 公开了一种执行口袋或晕轮植入物的改进方法。 通过增加漏电流，降低噪声容限和增加最小栅极电压，由晕轮植入物造成的损伤和缺陷的量会降低半导体器件的性能。 卤素或分组注入在冷温度下进行，这降低了对晶体结构的损害，并改善了晶体的非晶化。 使用冷温度还允许使用较轻的元素用于卤素注入，例如硼或磷。