公开(公告)号：US09431241B2

公开(公告)日：2016-08-30

申请号：US14411999

申请日：2013-07-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zhanxin Li

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/505

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/02211

Abstract: A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below 350° C. to produce and deposit a silicon nitride thin film, wherein a rate of charging silane is 300-350 sccm, a rate of charging ammonia gas is 1000 sccm, a rate of charging nitrogen gas is 1000 sccm; a power of a high frequency source is 0.15˜0.30 KW, a power of a low frequency source is 0.15˜0.30 KW; a reaction pressure is 2.3˜2.6 Torr; a reaction duration is 4˜6 s. The above method for manufacturing a silicon nitride thin film provides a preferable parameter range and preferred parameters for generating a low-stress SIN thin film at low temperatures, achieves manufacture of a low-stress SIN thin film at low temperatures, and thus, better satisfies the situation requiring a low-stress SIN thin film.

Abstract translation: 制造氮化硅薄膜的方法包括在低于350℃的环境温度下加入硅烷，氨气和氮气以产生和沉积氮化硅薄膜的步骤，其中填充硅烷的速率为300-350 sccm，氨气的加入速率为1000sccm，氮气的充填速度为1000sccm; 高频源的功率为0.15〜0.30KW，低频源的功率为0.15〜0.30KW; 反应压力为2.3〜2.6乇; 反应时间为4〜6秒。 上述制造氮化硅薄膜的方法提供了优选的参数范围和用于在低温下产生低应力SIN薄膜的优选参数，在低温下实现了低应力SIN薄膜的制造，从而更好地满足 需要低应力SIN薄膜的情况。

公开(公告)号：US20160099347A1

公开(公告)日：2016-04-07

申请号：US14891470

申请日：2014-05-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shu Zhang ,  Guangtao Han ,  Guipeng Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/426 ,  H01L21/027

CPC classification number: H01L29/7816 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0274 ,  H01L21/28035 ,  H01L21/426 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a substrate of a wafer (S210); coating a photoresist on the surface of the wafer (S220); performing photoetching by using a first photoetching mask, and exposing a first implantation window after development (S230); performing ion implantation via the first implantation window to form a drift region in the substrate (S240); coating one layer of photoresist on the surface of the wafer again after removing the photoresist (S250); performing photoetching by using the photoetching mask of the oxide layer of the drift region (S260); and etching the oxide layer to form the oxide layer of the drift region (S270). Further provided is a laterally diffused metal oxide semiconductor device.

Abstract translation: 本发明提供一种横向扩散的金属氧化物半导体器件的制造方法，包括以下步骤：在晶片的基板上生长氧化物层（S210）; 在晶片的表面上涂覆光致抗蚀剂（S220）; 通过使用第一光刻掩模进行光蚀刻，以及在显影后曝光第一植入窗口（S230）; 经由所述第一注入窗进行离子注入以在所述衬底中形成漂移区（S240）; 在去除光致抗蚀剂之后再次在晶片表面上涂覆一层光致抗蚀剂（S250）; 通过使用漂移区域的氧化物层的光刻掩模来执行光刻（S260）; 并蚀刻氧化层以形成漂移区的氧化物层（S270）。 还提供了横向扩散的金属氧化物半导体器件。

公开(公告)号：US20150332981A1

公开(公告)日：2015-11-19

申请号：US14435955

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Anna ZHANG ,  Xiaoming LI

IPC: H01L21/66 ,  H01L21/683 ,  H01L21/3065

CPC classification number: H01L22/26 ,  H01L21/3065 ,  H01L21/6831

Abstract: A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.

Abstract translation: 在深硅沟槽蚀刻工艺中的晶片蚀刻方法包括以下步骤：a。 使用静电卡盘静电吸收晶片，并稳定工艺所需的气氛（S110）; b。 执行晶片主工艺的子步骤，并且主工艺的子步骤的时间比晶片主工艺所需的时间短; C。 释放静电吸盘在晶片上的静电吸附; d。 确定主处理的子步骤的累积时间是否达到预定阈值（如果是），执行步骤e（S150），如果不是则重复步骤a至c中的操作（S140）; 和e。 结束晶圆制造工艺。 蚀刻方法避免了晶片与静电卡盘的连续接触，减少了晶片表面上的静电积累，因此解决了DSIE工艺中晶片表面的抗网纹问题。

公开(公告)号：US20150227048A1

公开(公告)日：2015-08-13

申请号：US14435945

申请日：2013-09-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jiale Su

IPC: G03F7/20

CPC classification number: G03F7/2035 ,  G03F1/38 ,  G03F7/203

Abstract: A photolithography method and system based on a high step slope are provided. The method includes: S1, manufacturing a sacrificial layer with a high step slope on a substrate; S2, adopting a spin-on PR coating process to cover the sacrificial layer with a photoresist layer to form a photolithographic layer; S3, forming a mask pattern and a compensation pattern on a mask; and S4, performing photolithography processes, by a photolithography machine, on the photolithographic layer. By forming a slope-top compensation pattern and a slope compensation pattern on a mask to perform photolithography on the substrate of a sacrificial layer, a relatively wide compensation pattern is set in a part of the top of the slope with a small thickness, thereby compensating the overexposure at the top of the slope, reducing the error in the photolithographic pattern, and improving the precision of photolithography of the high step slope.

Abstract translation: 提供了一种基于高阶斜率的光刻方法和系统。 该方法包括：S1，在衬底上制造具有高阶跃斜率的牺牲层; S2，采用旋涂PR涂覆工艺以用光致抗蚀剂层覆盖牺牲层以形成光刻层; S3，在掩模上形成掩模图案和补偿图案; 和S4，通过光刻机在光刻层上进行光刻工艺。 通过在掩模上形成斜坡补偿图案和斜率补偿图案以在牺牲层的基板上进行光刻，在斜面的顶部的一部分中以较小的厚度设置相对较宽的补偿图案，从而补偿 斜坡顶部过度曝光，降低了光刻图案的误差，提高了高阶斜坡光刻的精度。

公开(公告)号：US20150179437A1

公开(公告)日：2015-06-25

申请号：US14411999

申请日：2013-07-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zhanxin Li

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/505 ,  H01L21/0217 ,  H01L21/02211

Abstract: A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below 350° C. to produce and deposit a silicon nitride thin film, wherein a rate of charging silane is 300-350 sccm, a rate of charging ammonia gas is 1000 sccm, a rate of charging nitrogen gas is 1000 sccm; a power of a high frequency source is 0.15˜0.30 KW, a power of a low frequency source is 0.15˜0.30 KW; a reaction pressure is 2.3˜2.6 Torr; a reaction duration is 4˜6 s. The above method for manufacturing a silicon nitride thin film provides a preferable parameter range and preferred parameters for generating a low-stress SIN thin film at low temperatures, achieves manufacture of a low-stress SIN thin film at low temperatures, and thus, better satisfies the situation requiring a low-stress SIN thin film.

Abstract translation: 制造氮化硅薄膜的方法包括在低于350℃的环境温度下加入硅烷，氨气和氮气以产生和沉积氮化硅薄膜的步骤，其中填充硅烷的速率为300-350 sccm，氨气的加入速率为1000sccm，氮气的充填速度为1000sccm; 高频源的功率为0.15〜0.30KW，低频源的功率为0.15〜0.30KW; 反应压力为2.3〜2.6乇; 反应时间为4〜6秒。 上述制造氮化硅薄膜的方法提供了优选的参数范围和用于在低温下产生低应力SIN薄膜的优选参数，在低温下实现了低应力SIN薄膜的制造，从而更好地满足 需要低应力SIN薄膜的情况。

公开(公告)号：US20140329385A1

公开(公告)日：2014-11-06

申请号：US14351828

申请日：2012-10-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD

Inventor： Hsiao-Chia Wu ,  Shilin Fang ,  Tse-Huang Lo ,  Zhengpei Chen ,  Shu Zhang

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76837 ,  H01L21/76838 ,  H01L24/03

Abstract: A method for manufacturing a semiconductor thick metal structure includes a thick metal deposition step, a metal patterning step, and a passivation step. In the thick metal deposition step, a Ti—TiN laminated structure is used as an anti-reflection layer to implement 4 μm metal etching without residue. In the metal patterning step, N2 is used for the protection of a sidewall to implement on a 4 μm metal concave-convex structure a tilt angle of nearly 90 degrees, and a main over-etching step is added to implement the smoothness of the sidewall of the 4 μm metal concave-convex structure. A half-filled passivation filling structure is used to implement effective passivation protection of 1.5 um metal gaps having less than 4 um of metal thickness. Manufacturing of the 4 μm thick metal structure having a linewidth/gap of 1.5 μm/1.5 μm is finally implemented.

Abstract translation: 一种制造半导体厚金属结构体的方法包括厚金属沉积步骤，金属图案化步骤和钝化步骤。 在厚金属沉积步骤中，使用Ti-TiN层压结构作为抗反射层，以实现无残留的4μm金属蚀刻。 在金属图案化步骤中，使用N 2来保护侧壁以在接近90度的倾斜角度的4μm金属凹凸结构上实施，并且添加主过蚀刻步骤以实现侧壁的平滑度 的4μm金属凹凸结构。 使用半填充钝化填充结构来实现具有小于4μm的金属厚度的1.5um金属间隙的有效钝化保护。 最终实现线宽/间隙为1.5μm/1.5μm的4μm厚的金属结构体的制造。

公开(公告)号：US20140145290A1

公开(公告)日：2014-05-29

申请号：US14130449

申请日：2012-10-23

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Lihui Gu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/872

CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/10 ,  H01L29/402 ,  H01L29/66143 ,  H01L29/872

Abstract: A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.

Abstract translation: 公开了一种高电压肖特基二极管及其制造方法。 二极管包括：P型衬底和两个N型埋层，第一N型掩埋层位于阴极引出区下方，第二N型掩埋层位于阴极区下面; 外延层; 位于外延层上的两个N型阱区，第一N型阱区是横向漂移区，并具有阴极引出区，第二N型阱区位于第二N 型埋层，是阴极区; 位于所述第二N型掩埋层上并围绕所述阴极区的第一P型阱区; 位于所述横向漂移区上的场氧化物隔离区; 位于阴极区域的阳极和位于阴极引出区域的表面上的阴极。

公开(公告)号：US20140138740A1

公开(公告)日：2014-05-22

申请号：US14130481

申请日：2013-04-27

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Yonghai Hu ,  Meng Dai ,  Zhongyu Lin ,  Guangyang Wang

IPC: H01L27/02 ,  H01L21/762 ,  H01L21/8232

CPC classification number: H01L27/0255 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/32055 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/8232 ,  H01L27/0248 ,  H01L29/402 ,  H01L29/66121 ,  H01L29/87

Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

Abstract translation: 静电放电保护结构包括：第一导电类型的衬底，第二导电类型的阱区，衬底中的衬底接触区域和第一类型的导电性，阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性，衬底反掺杂区域和第二类型的导电性，衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性，通信 在衬底和阱区之间的横向结合处的区域，衬底反掺杂区域和连通区域之间的第一隔离区域，阱对掺杂区域和连通区域之间的第二隔离区域， 第一隔离区和衬底上的另一端，以及氧化物层上的场板结构。

公开(公告)号：US10816903B2

公开(公告)日：2020-10-27

申请号：US15905969

申请日：2018-02-27

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jiale Su

IPC: G03F7/20 ,  G03F1/70 ,  G03F1/38

Abstract: A photolithography system based on a high step slope may include a depositing unit configured to manufacture a sacrificial layer having high step slope on a substrate. The system may also include a coating unit configured to coat a photoresist layer on the sacrificial layer by performing a spin-on PR coating process to form a photolithographic layer. The system may further include a photolithography unit configured to perform one or more photolithography processes to the photolithographic layer. The photolithography unit may comprise a plurality of masks of compensation patterns. The compensation pattern may comprise a slope-top compensation pattern and a slope compensation pattern.

公开(公告)号：US10062746B2

公开(公告)日：2018-08-28

申请号：US15539554

申请日：2015-09-10

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shengrong Zhong ,  Xiaoshe Deng ,  Dongfei Zhou

IPC: H01L29/06 ,  H01L21/78 ,  H01L21/02 ,  H01L21/04 ,  H01L29/861 ,  H02M3/158 ,  H01L21/768

Abstract: A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.