Electrostatic Discharge Protection Structure And Fabrication Method Thereof
    2.
    发明申请
    Electrostatic Discharge Protection Structure And Fabrication Method Thereof 有权
    静电放电保护结构及其制作方法

    公开(公告)号:US20140138740A1

    公开(公告)日:2014-05-22

    申请号:US14130481

    申请日:2013-04-27

    Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

    Abstract translation: 静电放电保护结构包括:第一导电类型的衬底,第二导电类型的阱区,衬底中的衬底接触区域和第一类型的导电性,阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性,衬底反掺杂区域和第二类型的导电性,衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性,通信 在衬底和阱区之间的横向结合处的区域,衬底反掺杂区域和连通区域之间的第一隔离区域,阱对掺杂区域和连通区域之间的第二隔离区域, 第一隔离区和衬底上的另一端,以及氧化物层上的场板结构。

    Electrostatic Discharge Protection Structure And Fabrication Method Thereof
    3.
    发明申请
    Electrostatic Discharge Protection Structure And Fabrication Method Thereof 审中-公开
    静电放电保护结构及其制作方法

    公开(公告)号:US20160181237A1

    公开(公告)日:2016-06-23

    申请号:US15055613

    申请日:2016-02-28

    Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

    Abstract translation: 静电放电保护结构包括:第一导电类型的衬底,第二导电类型的阱区,衬底中的衬底接触区域和第一类型的导电性,阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性,衬底反掺杂区域和第二类型的导电性,衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性,通信 在衬底和阱区之间的横向结合处的区域,衬底反掺杂区域和连通区域之间的第一隔离区域,阱对掺杂区域和连通区域之间的第二隔离区域, 第一隔离区和衬底上的另一端,以及氧化物层上的场板结构。

    SEMICONDUCTOR DEVICE FOR ESD PROTECTION
    4.
    发明申请
    SEMICONDUCTOR DEVICE FOR ESD PROTECTION 有权
    用于ESD保护的半导体器件

    公开(公告)号:US20150162286A1

    公开(公告)日:2015-06-11

    申请号:US14411550

    申请日:2012-10-22

    Abstract: A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.

    Abstract translation: 用于静电放电保护的半导体器件包括衬底,形成在衬底中的第一阱和第二阱。 第一和第二阱分别并列形成,在界面处相遇,分别具有第一导电型和第二导电型。 在第一阱中形成第一重掺杂区和第二重掺杂区。 在第二阱中形成第三重掺杂区和第四重掺杂区。 第一,第二,第三和第四重掺杂区域分别具有第一,第二,第二和第一导电类型。 第一和第二重掺杂区域的位置沿平行于界面的方向错开。

    Electrostatic discharge protection structure and fabrication method thereof
    5.
    发明授权
    Electrostatic discharge protection structure and fabrication method thereof 有权
    静电放电保护结构及其制造方法

    公开(公告)号:US09343454B2

    公开(公告)日:2016-05-17

    申请号:US14130481

    申请日:2013-04-27

    Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

    Abstract translation: 静电放电保护结构包括:第一导电类型的衬底,第二导电类型的阱区,衬底中的衬底接触区域和第一类型的导电性,阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性,衬底反掺杂区域和第二类型的导电性,衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性,通信 在衬底和阱区之间的横向结合处的区域,衬底反掺杂区域和连通区域之间的第一隔离区域,阱对掺杂区域和连通区域之间的第二隔离区域, 第一隔离区和衬底上的另一端,以及氧化物层上的场板结构。

    Semiconductor device for ESD protection
    6.
    发明授权
    Semiconductor device for ESD protection 有权
    用于ESD保护的半导体器件

    公开(公告)号:US09202790B2

    公开(公告)日:2015-12-01

    申请号:US14411550

    申请日:2012-10-22

    Abstract: A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.

    Abstract translation: 用于静电放电保护的半导体器件包括衬底,形成在衬底中的第一阱和第二阱。 第一和第二阱分别并列形成,在界面处相遇,分别具有第一导电型和第二导电型。 在第一阱中形成第一重掺杂区和第二重掺杂区。 在第二阱中形成第三重掺杂区和第四重掺杂区。 第一,第二,第三和第四重掺杂区域分别具有第一,第二,第二和第一导电类型。 第一和第二重掺杂区域的位置沿平行于界面的方向错开。

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