公开(公告)号：US20100232744A1

公开(公告)日：2010-09-16

申请号：US12785786

申请日：2010-05-24

Applicant: Motoo ASAI ,  Hiroaki Kodama ,  Toyoaki Tanaka

Inventor： Motoo ASAI ,  Hiroaki Kodama ,  Toyoaki Tanaka

IPC: G02B6/12

CPC classification number: G02B6/43 ,  H01L24/73 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01088 ,  H01L2924/01322 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H05K1/0274 ,  H05K3/28 ,  H05K3/4602 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A device for optical communication including a substrate for mounting an IC chip, and a multilayered printed circuit board. An optical path for transmitting optical signal which penetrates the substrate for mounting an IC chip is formed in the substrate for mounting an IC chip.

Abstract translation: 一种用于光通信的装置，包括用于安装IC芯片的基板和多层印刷电路板。 在用于安装IC芯片的基板中形成有用于透射用于安装IC芯片的基板的用于透射光信号的光路。

公开(公告)号：US07761984B2

公开(公告)日：2010-07-27

申请号：US12053237

申请日：2008-03-21

Applicant: Yasuji Hiramatsu ,  Motoo Asai ,  Naohiro Hirose ,  Takashi Kariya

Inventor： Yasuji Hiramatsu ,  Motoo Asai ,  Naohiro Hirose ,  Takashi Kariya

IPC: H01K3/10

CPC classification number: H05K3/4679 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/0082 ,  H05K3/421 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/0554 ,  Y10S430/146 ,  Y10T29/49004 ,  Y10T29/49082 ,  Y10T29/49085 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A multi-layer printed wiring board includes a board covered with a conductor layer, an interlayer insulating resin layer, an etched metal film on the interlayer insulating resin layer, and a via hole. The interlayer insulating resin layer has a fibrous substrate. The via hole has an electrolytic plated film and an electrolessly plated film and connects the conductor layer of the board and the etched metal film.

Abstract translation: 多层印刷电路板包括覆盖有导体层的基板，层间绝缘树脂层，层间绝缘树脂层上的蚀刻金属膜和通孔。 层间绝缘树脂层具有纤维基材。 通孔具有电解电镀膜和无电镀膜，并且连接板的导体层和蚀刻的金属膜。

公开(公告)号：US07712212B2

公开(公告)日：2010-05-11

申请号：US11522961

申请日：2006-09-19

Applicant: Motoo Asai ,  Yasuji Hiramatsu

Inventor： Motoo Asai ,  Yasuji Hiramatsu

IPC: H01K3/10

CPC classification number: H05K3/108 ,  H05K1/0269 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4661 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2203/0307 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T156/1056 ,  Y10T428/24917

Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.

Abstract translation: 印刷电路板是通过在基板的导体电路上层叠层间绝缘层而形成的，其中导体电路由无电解电镀膜和电解电镀膜构成，并且在至少一部分上形成有粗糙层 导体电路的表面。

公开(公告)号：US20080285910A1

公开(公告)日：2008-11-20

申请号：US11750625

申请日：2007-05-18

Applicant: Kazuhito YAMADA ,  Tomohiro Nishikawa ,  Motoo Asai

Inventor： Kazuhito YAMADA ,  Tomohiro Nishikawa ,  Motoo Asai

IPC: G02B6/12

CPC classification number: G02B6/43 ,  G02B6/12002 ,  H01L2224/16145 ,  H01L2224/24 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K1/0274 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4691 ,  H05K2201/09536

Abstract: The photoelectric circuit board according to the present invention is a photoelectric circuit board, wherein a rigid portion where at least a conductor circuit and an insulating layer are formed and layered and one or more flex portions that are bendable are integrated, external connection portions for mounting an optical element and/or a package substrate on which an optical element is mounted are formed in above-described rigid portion, and an optical circuit is formed in at least one of above-described flex portions.

Abstract translation: 根据本发明的光电电路板是光电电路板，其中至少形成导体电路和绝缘层并且层叠有一个或多个可弯曲的弯曲部分的刚性部分被集成，用于安装的外部连接部分 在上述刚性部分中形成有安装有光学元件的光学元件和/或封装基板，并且在至少一个上述弯曲部分中形成光电路。

公开(公告)号：US07437030B2

公开(公告)日：2008-10-14

申请号：US11402084

申请日：2006-04-12

Applicant: Motoo Asai ,  Hiroaki Kodama

Inventor： Motoo Asai ,  Hiroaki Kodama

IPC: G02B6/00

CPC classification number: G02B6/4204 ,  G02B6/4214 ,  G02B6/4232 ,  G02B6/43 ,  H01L31/0203 ,  H01L31/02327 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H05K1/0274 ,  H05K3/4602 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The present invention aims to provide a substrate for mounting an IC chip, on which an optical signal passing region is formed and which can suppress a transmission loss in an optical signal and transmit an optical signal more positively with high reliability. The substrate for mounting an IC chip according to the present invention is a substrate for mounting an IC chip, in which a conductor circuit and an insulating layer are laminated in alternate fashion and in repetition on both faces of a substrate and an optical element is mounted on the substrate. Herein, the substrate for mounting an IC chip includes an optical signal passing region, and a microlens arranged on an end portion of the optical signal passing region on the opposite side from the optical element.

Abstract translation: 本发明的目的在于提供一种用于安装IC芯片的基板，其上形成有光信号通过区域，并且可以抑制光信号中的传输损耗并且以高可靠性更积极地发送光信号。 根据本发明的用于安装IC芯片的基板是用于安装IC芯片的基板，其中导体电路和绝缘层在基板的两个表面上以交替的方式并且重复地层叠并且安装有光学元件 在基板上。 这里，用于安装IC芯片的基板包括光信号通过区域和布置在与光学元件相反侧的光信号通过区域的端部上的微透镜。

公开(公告)号：US20080170819A1

公开(公告)日：2008-07-17

申请号：US11623923

申请日：2007-01-17

Applicant: Hiroaki Kodama ,  Motoo Asai

Inventor： Hiroaki Kodama ,  Motoo Asai

IPC: G02B6/12

CPC classification number: G02B6/43 ,  G02B6/138 ,  G02B6/4204 ,  G02B6/4246 ,  H01L27/14618 ,  H01L27/14627 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An optical element of the present invention comprises: one or a plurality of unit elements having a plurality of external electrodes formed on one main surface thereof, wherein upon taking the one main surface of the unit elements in a plan view, the plurality of external electrodes are locally formed in a first region of two regions of a planar shape of the main surface, the two region formed by equally dividing the planar shape with a center line.

Abstract translation: 本发明的光学元件包括：一个或多个单元元件，其具有形成在其一个主表面上的多个外部电极，其中，在将单元元件的一个主表面放置在平面图中时，多个外部电极 局部地形成在主表面的平面形状的两个区域的第一区域中，该两个区域通过将平面形状等分成中心线而形成。

公开(公告)号：US20080142255A1

公开(公告)日：2008-06-19

申请号：US12033455

申请日：2008-02-19

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/16

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract translation: 片状电容器20设置在印刷电路板10的芯基板30中。 这使得可以缩短IC芯片90和芯片电容器20之间的距离并减小环路电感。 由于通过以多层方式设置第一树脂基板30a，第二树脂基板30b和第三树脂基板30c构成的芯基板30d，因此芯基板30可以获得足够的强度。

公开(公告)号：US20080023815A1

公开(公告)日：2008-01-31

申请号：US11858942

申请日：2007-09-21

Applicant: Motoo ASAI ,  Kouta Noda ,  Yasushi Inagaki

Inventor： Motoo ASAI ,  Kouta Noda ,  Yasushi Inagaki

IPC: H01L23/24

CPC classification number: H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/005 ,  H05K3/045 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0245 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1152 ,  H05K2203/1189 ,  Y10T428/25 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A printed wiring board including a substrate, conductor circuits and interlayer dielectric layers stacked alternately on the substrate, each of the interlayer dielectric layers including a curable resin having flaky particles dispersed therein, and viaholes formed in the interlayer dielectric layers and electrically connecting the conductor circuits at different levels.

Abstract translation: 一种印刷电路板，包括基板，导体电路和层间电介质层，层叠电介质层交替地堆叠在基板上，每个层间介电层包括其中分散有片状颗粒的固化树脂，以及形成在层间电介质层中的通孔，并将导体电路 在不同层次上

公开(公告)号：US20070258225A1

公开(公告)日：2007-11-08

申请号：US11777841

申请日：2007-07-13

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract translation: 片状电容器20设置在印刷电路板10的芯基板30中。 这使得可以缩短IC芯片90和芯片电容器20之间的距离并减小环路电感。 由于通过以多层方式设置第一树脂基板30a，第二树脂基板30b和第三树脂基板30c构成的芯基板30d，因此芯基板30可以获得足够的强度。

公开(公告)号：US07071424B1

公开(公告)日：2006-07-04

申请号：US09600890

申请日：1999-02-05

Applicant: Seiji Shirai ,  Kenichi Shimada ,  Motoo Asai

Inventor： Seiji Shirai ,  Kenichi Shimada ,  Motoo Asai

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/381 ,  H05K3/382 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/0278 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/31681

Abstract: The present invention provides a multilayer printed wiring board having a filled viahole structure advantageously usable for forming a fine circuit pattern thereon, and having an excellent resistance against cracking under a thermal shock or due to heat cycle. The multilayer printed wiring board is comprised of conductor circuitry layers and interlaminar insulative resin layers deposited alternately one on another, the interlaminar insulative resin layers each having formed through them holes each filled with a plating layer to form a viahole. The surface of the plating layer exposed out of the hole for the viahole is formed substantially flat and lies at a substantially same level as the surface of the conductor circuit disposed in the interlaminar insulative resin layer. The thickness of the conductor circuitry layer is less than a half of the viahole diameter and less than 25 μm. The inner wall of the hole formed in the interlaminar insulative resin layer is roughened and an electroless plating layer is deposited on the roughened surface. An electroplating layer is filled in the hole including the electroless plating layer to form the viahole. The interlaminar insulative resin layer is formed from a composite of a fluororesin showing a high fracture toughness and a heat-resistant thermoplastic resin, a composite of fluororesin and thermosetting resin or a composite of thermosetting and thermoplastic resins.

Abstract translation: 本发明提供了一种多层印刷线路板，其具有有利地用于在其上形成精细电路图案的填充通孔结构，并且在热冲击下或由于热循环具有优异的抗开裂性。 多层印刷布线板由交替地彼此堆叠的导体电路层和层间绝缘树脂层构成，层间绝缘树脂层各自形成有各自填充有镀层的孔，以形成通孔。 露出用于通孔的孔的镀层的表面形成为基本上平坦，并且位于与布置在层间绝缘树脂层中的导体电路的表面基本相同的水平。 导体电路层的厚度小于通孔直径的一半，小于25μm。 形成在层间绝缘树脂层中的孔的内壁变粗糙，并且在粗糙化表面上沉积化学镀层。 在包括无电镀层的孔中填充电镀层以形成通孔。 层间绝缘树脂层由显示高断裂韧性的氟树脂和耐热性热塑性树脂，氟树脂和热固性树脂的复合物或热固性和热塑性树脂的复合材料的复合材料形成。