SOFT MATERIAL WAFER BONDING AND METHOD OF BONDING
    11.
    发明申请
    SOFT MATERIAL WAFER BONDING AND METHOD OF BONDING 有权
    软质材料的粘结和粘结方法

    公开(公告)号:US20130207098A1

    公开(公告)日:2013-08-15

    申请号:US13371198

    申请日:2012-02-10

    CPC classification number: H01L21/2007 H01L21/67092 H01L27/1464

    Abstract: A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer.

    Abstract translation: 一种半导体器件,包括具有第一衬底和第一衬底上的第一氧化物层的第一晶片组件。 半导体器件还包括第二晶片组件,其具有第二衬底和在第二衬底上的第二氧化物层。 第一氧化物层和第二氧化物层通过范德华力键或共价键键合在一起。 一种接合第一晶片组件和第二晶片组件的方法,包括在第一衬底上形成第一氧化物层。 该方法还包括在第二晶片组件上形成第二氧化物层。 该方法还包括在第一氧化物层和第二氧化物层之间形成范德华氏键或共价键。

    WAFER AND METHOD OF PROCESSING WAFER
    12.
    发明申请
    WAFER AND METHOD OF PROCESSING WAFER 有权
    WAFER和WAFER加工方法

    公开(公告)号:US20130154060A1

    公开(公告)日:2013-06-20

    申请号:US13328346

    申请日:2011-12-16

    CPC classification number: H01L21/02087 H01L21/76802 H01L21/76883

    Abstract: A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.

    Abstract translation: 公开了一种包括衬底,在衬底上的电介质层和介电层上的导电层的晶片。 基板具有主要部分。 电介质层的周边和基板的主要部分的周边分开第一距离。 导电层的周边和基板的主要部分的周边分开第二距离。 所述第二距离的范围从小于所述第一距离的所述基板的直径的0.5%的值的大约为大于所述第一距离的直径的0.5%的值。

    Test device and method for laser alignment calibration
    13.
    发明授权
    Test device and method for laser alignment calibration 有权
    用于激光对准校准的测试装置和方法

    公开(公告)号:US07304728B2

    公开(公告)日:2007-12-04

    申请号:US10942554

    申请日:2004-09-15

    CPC classification number: H01L22/34 G01B21/042

    Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

    Abstract translation: 一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。 测试装置包括具有包括目标点的校准图案的激光敏感材料。 当工具被正确调整时,激光束撞击目标点并释放到生产中。 如果激光束错过目标点,则重新调整工具并重新测试直到激光束撞击目标点。

    Removal of SiON residue after CMP
    14.
    发明授权
    Removal of SiON residue after CMP 失效
    CMP后去除SiON残留物

    公开(公告)号:US06828226B1

    公开(公告)日:2004-12-07

    申请号:US10042573

    申请日:2002-01-09

    Abstract: For 0.18 micron technology, it is common practice to use silicon oxynitride as an anti-reflective layer for defining the via etch patterns. It has however been found that, using current technology, residual particles of oxynitride get left behind. The present invention solves this problem by subjecting the surface from which the silicon oxynitride was removed to a high pressure rinse of an aqueous solution that includes a surfactant such as tetramethyl ammonium hydroxide or isopropyl alcohol. These surfactants serve to modify the hydrophobic behavior of the silicon oxynitride particles so that they no longer cling to the surface.

    Abstract translation: 对于0.18微米技术,通常的做法是使用氮氧化硅作为抗反射层来定义通孔蚀刻图案。 然而,已经发现,使用当前的技术,留下残留的氮氧化物颗粒。 本发明通过将去除了氮氧化硅的表面经受包括诸如四甲基氢氧化铵或异丙醇的表面活性剂的水溶液的高压冲洗来解决这个问题。 这些表面活性剂用于改变氮氧化硅颗粒的疏水性能,使得它们不再粘附到表面。

    Apparatus and method for removing coating layers from alignment marks
    15.
    发明授权
    Apparatus and method for removing coating layers from alignment marks 有权
    用于从对准标记去除涂层的装置和方法

    公开(公告)号:US06682605B2

    公开(公告)日:2004-01-27

    申请号:US10043017

    申请日:2002-01-07

    CPC classification number: H01L21/67051 B08B3/02 H01L21/32134 Y10S134/902

    Abstract: An apparatus and a method for removing coating layers from the top of alignment marks on a wafer are described. The apparatus includes a cleaning chamber that is a cavity and a lid member suspended in the cavity, a wafer chuck that is rotatably mounted in the lid member for holding a wafer in an upside down position such that the alignment marks are facing downwardly, and at least two solvent dispensing arms mounted in an outer peripheral area of the lid member that are immediately adjacent to the chuck for dispensing a flow of solvent upwardly toward the active surface of the wafer when the wafer is held in a stationary position, each of the at least two solvent dispensing arms are positioned corresponding to a position of one of the alignment marks.

    Abstract translation: 描述了从晶片上的对准标记的顶部去除涂层的设备和方法。 该装置包括一个作为空腔的清洁室和悬挂在空腔中的盖构件,可旋转地安装在盖构件中的晶片卡盘,用于将晶片保持在倒置位置,使得对准标记面向下,并且在 至少两个溶剂分配臂安装在盖构件的外周区域中,其紧邻卡盘,用于当晶片保持在静止位置时向上朝向晶片的有效表面分配溶剂流, 至少两个溶剂分配臂对应于一个对准标记的位置定位。

    Planarization of shallow trench isolation (STI)
    16.
    发明授权
    Planarization of shallow trench isolation (STI) 有权
    浅沟槽隔离(STI)的平面化

    公开(公告)号:US06645825B1

    公开(公告)日:2003-11-11

    申请号:US09614554

    申请日:2000-07-12

    CPC classification number: H01L21/76229

    Abstract: An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.

    Abstract translation: 已经开发了一种用于制造嵌入硅衬底中的浅沟槽隔离(STI)的平面化结构的改进和新工艺。 平面化方法包括两步CMP工艺,其中第一CMP步骤包括使用对氧化硅选择性的第一抛光浆料进行二氧化硅的化学机械抛光。 通过基于沟槽占据的衬底面积的百分比来选择过抛光厚度来确定第二CMP步骤的时间。 实现了高的制造成品率和优异的氧化硅STI平坦度。

    EXTERNAL DEVICE WITH A DRIVER AUTO-RUN INSTALLATION AND METHOD THEREOF
    19.
    发明申请
    EXTERNAL DEVICE WITH A DRIVER AUTO-RUN INSTALLATION AND METHOD THEREOF 审中-公开
    具有驱动器自动运行安装的外部设备及其方法

    公开(公告)号:US20090193152A1

    公开(公告)日:2009-07-30

    申请号:US12264233

    申请日:2008-11-03

    CPC classification number: G06F13/102 G06F9/4413

    Abstract: An external device includes a controller, a connector, a function circuit, and a storage device. The storage device stores firmware and an image file. The image file includes an installation program and a driver. The external device is coupled to a host via the connector. The firmware can drive the controller to generate a virtual optical disc drive in the host and load the image file to the virtual optical disc drive so as to start the installation program. When the host does not have the driver, the installation program can install the driver in the host. When the host has the driver, the host can drive the function circuit to work.

    Abstract translation: 外部设备包括控制器,连接器,功能电路和存储设备。 存储设备存储固件和图像文件。 图像文件包括安装程序和驱动程序。 外部设备经由连接器耦合到主机。 固件可以驱动控制器在主机中生成虚拟光盘驱动器,并将映像文件加载到虚拟光盘驱动器,以启动安装程序。 当主机没有驱动程序时,安装程​​序可以将驱动程序安装在主机中。 当主机有驱动程序时,主机可以驱动功能电路工作。

    Catch-pin water support for process chamber
    20.
    发明授权
    Catch-pin water support for process chamber 失效
    捕捉针水处理室支撑

    公开(公告)号:US06863491B2

    公开(公告)日:2005-03-08

    申请号:US10339691

    申请日:2003-01-08

    CPC classification number: H01L21/68707 Y10T279/1033 Y10T279/1291 Y10T279/19

    Abstract: A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.

    Abstract translation: 一种新的和改进的晶片支撑件,用于在诸如边缘珠去除(EBR)室的处理室中支撑晶片。 晶片支撑件包括多个晶片支撑单元,每个晶片支撑单元包括接合晶片的边缘部分或斜面的夹持块。 夹持块附接到接合和分离机构,用于选择性地使夹持器块与晶片接合以支撑晶片,并且将夹持器块与晶片分离,以释放晶片以从晶片移除。 夹持器块几乎不接触晶片的图案化表面上的表面积,以防止或基本上减少晶片上接触引起的缺陷的形成。

Patent Agency Ranking