公开(公告)号：US20100332013A1

公开(公告)日：2010-12-30

申请号：US12826562

申请日：2010-06-29

Applicant: Brian D. Choi ,  Gunsu Yun ,  Vijayakumar C. Venugopal

Inventor： Brian D. Choi ,  Gunsu Yun ,  Vijayakumar C. Venugopal

IPC: G06F19/00

CPC classification number: G05B23/0254 ,  G05B2219/37224

Abstract: A method for predicting etch rate uniformity for qualifying health status of a processing chamber during substrate processing of substrates is provided. The method includes executing a recipe and receiving processing data from a first set of sensors. The method further includes analyzing the processing data utilizing a subsystem health check predictive model to determine calculated data, which includes at least one of etch rate data and uniformity data. The subsystem health check predictive model is constructed by correlating measurement data from a set of film substrates with processing data collected during analogous processing of a set of non-film substrates. The method yet also includes performing a comparison of the calculated data against a set of control limits as defined by the subsystem health check predictive model. The method yet further includes generating a warning if the calculated data is outside of the set of control limits.

Abstract translation: 提供了一种用于在衬底的衬底处理期间预测用于限定处理室的健康状况的蚀刻速率均匀性的方法。 该方法包括执行食谱并从第一组传感器接收处理数据。 该方法还包括利用子系统健康检查预测模型来分析处理数据，以确定计算出的数据，其包括蚀刻速率数据和均匀性数据中的至少一个。 通过将来自一组膜基底的测量数据与在一组非膜基底的类似处理期间收集的处理数据相关联来构建子系统健康检查预测模型。 该方法还包括执行计算数据与由子系统健康检查预测模型定义的一组控制限制的比较。 该方法还包括如果所计算的数据超出该组控制限制，则产生警告。

公开(公告)号：US20100332012A1

公开(公告)日：2010-12-30

申请号：US12555674

申请日：2009-09-08

Applicant: Chung-Ho Huang ,  Vijayakumar C. Venugopal ,  Connie Lam ,  Dragan Podlesnik

Inventor： Chung-Ho Huang ,  Vijayakumar C. Venugopal ,  Connie Lam ,  Dragan Podlesnik

IPC: G05B9/02 ,  G06F9/50 ,  G06F11/20

CPC classification number: G06F9/5027 ,  G05B19/4184 ,  G05B2219/31202 ,  G05B2219/31293 ,  G05B2219/31318 ,  G05B2219/31481 ,  G05B2219/32209 ,  G05B2219/45031 ,  G06F11/2035 ,  G06F11/2043 ,  Y02P90/14 ,  Y02P90/18

Abstract: A process-level troubleshooting architecture (PLTA) configured to facilitate substrate processing in a plasma processing system is provided. The architecture includes a process module controller. The architecture also includes a plurality of sensors, wherein each sensor of the plurality of sensors communicates with the process module controller to collect sensed data about one or more process parameters. The architecture further includes a process-module-level analysis server, wherein the process-module-level analysis server communicates directly with the plurality of sensors and the process module controller. The process-module-level analysis server is configured for receiving data, wherein the data include at least one of the sensed data from the plurality of sensors and process module and chamber data from the process module controller. The process-module-level analysis server is also configured for analyzing the data and sending interdiction data directly to the process module controller when a problem is identified during the substrate processing.

Abstract translation: 提供了一种配置为促进等离子体处理系统中的基板处理的过程级故障排除架构（PLTA）。 该架构包括一个进程模块控制器。 该架构还包括多个传感器，其中多个传感器中的每个传感器与过程模块控制器通信以收集关于一个或多个过程参数的感测数据。 该体系结构还包括一个过程模块级分析服务器，其中过程模块级分析服务器与多个传感器和过程模块控制器直接通信。 过程模块级分析服务器被配置为用于接收数据，其中数据包括来自多个传感器的感测数据中的至少一个以及来自处理模块控制器的处理模块和室数据。 过程模块级分析服务器还被配置为当在衬底处理期间识别出问题时，分析数据并将拦截数据直接发送到过程模块控制器。

公开(公告)号：US20090002836A1

公开(公告)日：2009-01-01

申请号：US11772008

申请日：2007-06-29

Applicant: Vijayakumar C. Venugopal ,  Eric Pape

Inventor： Vijayakumar C. Venugopal ,  Eric Pape

IPC: G02B27/30

CPC classification number: H05H1/0025 ,  G02B27/30

Abstract: A method for optical interrogation of plasma during plasma processing in a plasma processing chamber is provided. The method includes providing an optical viewport. The method also includes providing a collimator arrangement. The collimator arrangement is configured with a plurality of collimators, wherein a first collimator of the plurality of collimators is separated by a connecting region from a second collimator in the plurality of collimators. The method further includes collecting optical signals, through the collimator arrangement, from the plasma within the plasma processing chamber while a substrate is being processed, resulting in highly collimated optical signals.

Abstract translation: 提供了一种在等离子体处理室中的等离子体处理期间对等离子体进行光询问的方法。 该方法包括提供光学视口。 该方法还包括提供准直器装置。 准直器装置配置有多个准直器，其中多个准直器中的第一准直仪由多个准直器中的第二准直器的连接区域分开。 该方法还包括在正在处理衬底的同时通过准直器装置从等离子体处理室内的等离子体收集光信号，导致高度准直的光信号。

公开(公告)号：US08983631B2

公开(公告)日：2015-03-17

申请号：US12555674

申请日：2009-09-08

Applicant: Chung Ho Huang ,  Vijayakumar C. Venugopal ,  Connie Lam ,  Dragan Podlesnik

Inventor： Chung Ho Huang ,  Vijayakumar C. Venugopal ,  Connie Lam ,  Dragan Podlesnik

IPC: G05B11/01 ,  G06F19/00 ,  G06F9/50 ,  G05B19/418 ,  G06F11/20

CPC classification number: G06F9/5027 ,  G05B19/4184 ,  G05B2219/31202 ,  G05B2219/31293 ,  G05B2219/31318 ,  G05B2219/31481 ,  G05B2219/32209 ,  G05B2219/45031 ,  G06F11/2035 ,  G06F11/2043 ,  Y02P90/14 ,  Y02P90/18

Abstract: A process-level troubleshooting architecture (PLTA) configured to facilitate substrate processing in a plasma processing system is provided. The architecture includes a process module controller. The architecture also includes a plurality of sensors, wherein each sensor of the plurality of sensors communicates with the process module controller to collect sensed data about one or more process parameters. The architecture further includes a process-module-level analysis server, wherein the process-module-level analysis server communicates directly with the plurality of sensors and the process module controller. The process-module-level analysis server is configured for receiving data, wherein the data include at least one of the sensed data from the plurality of sensors and process module and chamber data from the process module controller. The process-module-level analysis server is also configured for analyzing the data and sending interdiction data directly to the process module controller when a problem is identified during the substrate processing.

Abstract translation: 提供了一种配置为促进等离子体处理系统中的基板处理的过程级故障排除架构（PLTA）。 该架构包括一个进程模块控制器。 该架构还包括多个传感器，其中多个传感器中的每个传感器与过程模块控制器通信以收集关于一个或多个过程参数的感测数据。 该体系结构还包括一个过程模块级分析服务器，其中过程模块级分析服务器与多个传感器和过程模块控制器直接通信。 过程模块级分析服务器被配置为用于接收数据，其中数据包括来自多个传感器的感测数据中的至少一个以及来自处理模块控制器的处理模块和室数据。 过程模块级分析服务器还被配置为当在衬底处理期间识别出问题时，分析数据并将拦截数据直接发送到过程模块控制器。

公开(公告)号：US08650002B2

公开(公告)日：2014-02-11

申请号：US12499696

申请日：2009-07-08

Applicant: Brian Choi ,  Gunsu Yun ,  Vijayakumar C. Venugopal ,  Norman Williams

Inventor： Brian Choi ,  Gunsu Yun ,  Vijayakumar C. Venugopal ,  Norman Williams

IPC: B23Q17/00 ,  G06F17/40 ,  G06F19/00

CPC classification number: H01J37/32935

Abstract: A test system for facilitating determining whether a plasma processing system (which includes a plasma processing chamber) is ready for processing wafers. The test system may include a computer-readable medium storing at least a test program. The test program may include code for receiving electric parameter values derived from signals detected by at least one sensor when no plasma is present in the plasma processing chamber. The test program may also include code for generating electric model parameter values using the electric parameter values and a mathematical model. The test program may also include code for comparing the electric model parameter values with baseline model parameter value information. The test program may also include code for determining readiness of the plasma processing system based on the comparison. The test system may also include circuit hardware for performing one or more tasks associated with the test program.

Abstract translation: 用于有助于确定等离子体处理系统（其包括等离子体处理室）是否准备好用于处理晶片的测试系统。 测试系统可以包括至少存储测试程序的计算机可读介质。 测试程序可以包括用于接收由等离子体处理室中没有等离子体时由至少一个传感器检测到的信号导出的电参数值的代码。 测试程序还可以包括使用电参数值和数学模型产生电模型参数值的代码。 测试程序还可以包括用于将电模型参数值与基准模型参数值信息进行比较的代码。 测试程序还可以包括用于基于比较来确定等离子体处理系统的准备状态的代码。 测试系统还可以包括用于执行与测试程序相关联的一个或多个任务的电路硬件。

公开(公告)号：US08295966B2

公开(公告)日：2012-10-23

申请号：US12826562

申请日：2010-06-29

Applicant: Brian D Choi ,  Gunsu Yun ,  Vijayakumar C Venugopal

Inventor： Brian D Choi ,  Gunsu Yun ,  Vijayakumar C Venugopal

IPC: G06F19/00 ,  H01L21/00 ,  C23C16/00

CPC classification number: G05B23/0254 ,  G05B2219/37224

Abstract: A method for predicting etch rate uniformity for qualifying health status of a processing chamber during substrate processing of substrates is provided. The method includes executing a recipe and receiving processing data from a first set of sensors. The method further includes analyzing the processing data utilizing a subsystem health check predictive model to determine calculated data, which includes at least one of etch rate data and uniformity data. The subsystem health check predictive model is constructed by correlating measurement data from a set of film substrates with processing data collected during analogous processing of a set of non-film substrates. The method yet also includes performing a comparison of the calculated data against a set of control limits as defined by the subsystem health check predictive model. The method yet further includes generating a warning if the calculated data is outside of the set of control limits.

Abstract translation: 提供了一种用于在衬底的衬底处理期间预测用于限定处理室的健康状况的蚀刻速率均匀性的方法。 该方法包括执行食谱并从第一组传感器接收处理数据。 该方法还包括利用子系统健康检查预测模型来分析处理数据，以确定计算出的数据，其包括蚀刻速率数据和均匀性数据中的至少一个。 通过将来自一组膜基底的测量数据与在一组非膜基底的类似处理期间收集的处理数据相关联来构建子系统健康检查预测模型。 该方法还包括执行计算数据与由子系统健康检查预测模型定义的一组控制限制的比较。 该方法还包括如果所计算的数据超出该组控制限制，则产生警告。

公开(公告)号：US20100332168A1

公开(公告)日：2010-12-30

申请号：US12499696

申请日：2009-07-08

Applicant: Brian Choi ,  Gunsu Yun ,  Vijayakumar C. Venugopal ,  Norman Williams

Inventor： Brian Choi ,  Gunsu Yun ,  Vijayakumar C. Venugopal ,  Norman Williams

IPC: G01R27/00 ,  G06F19/00

CPC classification number: H01J37/32935

Abstract: A test system for facilitating determining whether a plasma processing system (which includes a plasma processing chamber) is ready for processing wafers. The test system may include a computer-readable medium storing at least a test program. The test program may include code for receiving electric parameter values derived from signals detected by at least one sensor when no plasma is present in the plasma processing chamber. The test program may also include code for generating electric model parameter values using the electric parameter values and a mathematical model. The test program may also include code for comparing the electric model parameter values with baseline model parameter value information. The test program may also include code for determining readiness of the plasma processing system based on the comparison. The test system may also include circuit hardware for performing one or more tasks associated with the test program.

Abstract translation: 用于有助于确定等离子体处理系统（其包括等离子体处理室）是否准备好用于处理晶片的测试系统。 测试系统可以包括至少存储测试程序的计算机可读介质。 测试程序可以包括用于接收由等离子体处理室中没有等离子体时由至少一个传感器检测到的信号导出的电参数值的代码。 测试程序还可以包括使用电参数值和数学模型产生电模型参数值的代码。 测试程序还可以包括用于将电模型参数值与基准模型参数值信息进行比较的代码。 测试程序还可以包括用于基于比较来确定等离子体处理系统的准备状态的代码。 测试系统还可以包括用于执行与测试程序相关联的一个或多个任务的电路硬件。

公开(公告)号：US07019844B2

公开(公告)日：2006-03-28

申请号：US10286410

申请日：2002-11-01

Applicant: Vijayakumar C. Venugopal ,  Andrew J. Perry

Inventor： Vijayakumar C. Venugopal ,  Andrew J. Perry

IPC: G01B9/02

CPC classification number: G01B11/0625 ,  G01B11/0683 ,  G01N21/8422

Abstract: A method of determining a parameter of interest during fabrication of a patterned substrate includes illuminating at least a portion of the patterned substrate with a normal incident light beam, obtaining a measured net reflectance spectrum of the portion of the patterned substrate from a normal reflected light beam, calculating a modeled net reflectance spectrum of the portion of the patterned substrate, and determining a set of parameters that provides a close match between the measured net reflectance spectrum and the modeled net reflectance spectrum. The modeled net reflectance spectrum is calculated as a weighted incoherent sum of reflectances from n≧1 different regions constituting the portion of the patterned substrate, wherein the reflectance of each of the n different regions is a weighted coherent sum of reflected fields from k≧1 laterally-distinct areas constituting the region.

Abstract translation: 在图案化衬底的制造期间确定感兴趣参数的方法包括用正常入射光束照射图案化衬底的至少一部分，从正常反射光束获得图案化衬底的部分的测量的净反射光谱 计算图案化衬底的部分的建模的净反射光谱，以及确定提供测量的净反射光谱和建模的净反射光谱之间的紧密匹配的一组参数。 模拟的净反射光谱被计算为构成图案化衬底部分的n≥1个不同区域的反射率的加权不相干和，其中n个不同区域中的每一个的反射率是来自k>的反射场的加权相干和， =构成该地区的1个横向不同的区域。

公开(公告)号：US08618807B2

公开(公告)日：2013-12-31

申请号：US12826568

申请日：2010-06-29

Applicant: Luc Albarede ,  Vijayakumar C Venugopal

Inventor： Luc Albarede ,  Vijayakumar C Venugopal

IPC: G01R31/00

CPC classification number: H01J37/32935 ,  G05B2219/31202

Abstract: A method for detecting an in-situ fast transient event within a processing chamber during substrate processing is provided. The method includes a set of sensors comparing a data set to a set of criteria (in-situ fast transient events) to determine if the first data set includes a potential in-situ fast transient event. If the first data set includes the potential in-situ fast transient event, the method also includes saving an electrical signature that occurs in a time period during which the potential in-situ fast transient event occurs. The method further includes comparing the electrical signature against a set of stored arc signatures. If a match is determined, the method yet also includes classifying the electrical signature as a first in-situ fast transient event and determining a severity level for the first in-situ fast transient event based on a predefined set of threshold ranges.

Abstract translation: 提供了一种用于在衬底处理期间检测处理室内的原位快速瞬变事件的方法。 该方法包括将数据集与一组标准（原位快速瞬变事件）进行比较的一组传感器，以确定第一数据集是否包括潜在的原位快速瞬变事件。 如果第一数据集包括潜在的原位快速瞬变事件，则该方法还包括保存在潜在的原位快速瞬变事件发生的时间段内发生的电特征。 该方法还包括将电特征与一组存储的电弧特征进行比较。 如果确定匹配，则该方法还包括将电特征分类为第一原位快速瞬时事件，并且基于预定义的一组阈值范围来确定第一原位快速瞬变事件的严重性级别。

公开(公告)号：US08538572B2

公开(公告)日：2013-09-17

申请号：US12826564

申请日：2010-06-29

Applicant: Jiangxin Wang ,  Andrew James Perry ,  Vijayakumar C Venugopal

Inventor： Jiangxin Wang ,  Andrew James Perry ,  Vijayakumar C Venugopal

IPC: G06F19/00 ,  G05B13/02 ,  H01L21/00 ,  G06F15/00

CPC classification number: H01J37/32963 ,  H01J37/32935

Abstract: A method for automatically identifying an optimal endpoint algorithm for qualifying a process endpoint during substrate processing within a plasma processing system is provided. The method includes receiving sensor data from a plurality of sensors during substrate processing of at least one substrate within the plasma processing system, wherein the sensor data includes a plurality of signal streams from a plurality of sensor channels. The method also includes identifying an endpoint domain, wherein the endpoint domain is an approximate period within which the process endpoint is expected to occur. The method further includes analyzing the sensor data to generate a set of potential endpoint signatures. The method yet also includes converting the set of potential endpoint signatures into a set of optimal endpoint algorithms. The method yet further includes importing one optimal endpoint algorithm of the set of optimal endpoint algorithms into production environment.

Abstract translation: 提供了一种用于在等离子体处理系统内的衬底处理期间自动识别用于限定过程端点的最佳端点算法的方法。 该方法包括在等离子体处理系统内至少一个衬底的衬底处理期间从多个传感器接收传感器数据，其中传感器数据包括来自多个传感器通道的多个信号流。 该方法还包括识别端点域，其中端点域是期望发生过程端点的近似周期。 该方法还包括分析传感器数据以产生一组潜在的端点签名。 该方法还包括将潜在端点签名的集合转换成一组最优端点算法。 该方法还包括将一组最优端点算法的一个最优端点算法导入到生产环境中。