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    3D chip sharing data bus
    12.
    发明授权
    3D chip sharing data bus 有权

    公开(公告)号：US12293993B2

    公开(公告)日：2025-05-06

    申请号：US18379925

    申请日：2023-10-13

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed

    IPC: H01L25/065 ,  H01L21/822 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H01L25/00 ,  H01L27/06 ,  H01L23/50

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    3D chip with shared clock distribution network
    13.
    发明授权
    3D chip with shared clock distribution network 有权

    公开(公告)号：US12142528B2

    公开(公告)日：2024-11-12

    申请号：US18146709

    申请日：2022-12-27

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

    IPC: H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    Direct-Bonded Native Interconnects And Active Base Die
    14.
    发明公开
    Direct-Bonded Native Interconnects And Active Base Die 审中-公开

    公开(公告)号：US20240265305A1

    公开(公告)日：2024-08-08

    申请号：US18379907

    申请日：2023-10-13

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Shaowu Huang ,  William C. Plants ,  David Edward Fisch

    IPC: G06N20/00 ,  G06V10/764 ,  G06V10/774

    CPC classification number: G06N20/00 ,  G06V10/764 ,  G06V10/774

    Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

    STACKED IC STRUCTURE WITH ORTHOGONAL INTERCONNECT LAYERS
    16.
    发明公开
    STACKED IC STRUCTURE WITH ORTHOGONAL INTERCONNECT LAYERS 审中-公开

    公开(公告)号：US20240234320A1

    公开(公告)日：2024-07-11

    申请号：US18399485

    申请日：2023-12-28

    Applicant: Adeia Semiconductor Inc.

    Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. DeLaCruz

    IPC: H01L23/528 ,  H01L21/822 ,  H01L23/00 ,  H01L23/50 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

    CPC classification number: H01L23/5286 ,  H01L21/8221 ,  H01L23/50 ,  H01L23/5225 ,  H01L24/26 ,  H01L25/0657 ,  H01L27/0688 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08147 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/15311

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

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