公开(公告)号：US11916076B2

公开(公告)日：2024-02-27

申请号：US16915140

申请日：2020-06-29

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. Delacruz ,  Don Draper ,  Jung Ko ,  Steven L. Teig

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2027/11838 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

公开(公告)号：US20240234424A1

公开(公告)日：2024-07-11

申请号：US18417446

申请日：2024-01-19

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Don Draper ,  Jung Ko ,  Steven L. Teig

IPC: H01L27/118 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L27/11807 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2027/11838 ,  H01L2027/11875 ,  H01L2027/11879 ,  H01L2027/11881

Abstract: The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.

公开(公告)号：US11515291B2

公开(公告)日：2022-11-29

申请号：US16397202

申请日：2019-04-29

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US11894345B2

公开(公告)日：2024-02-06

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/08 ,  H01L21/78 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06586 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/3025

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20230090121A1

公开(公告)日：2023-03-23

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US12278215B2

公开(公告)日：2025-04-15

申请号：US18399504

申请日：2023-12-28

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/552 ,  H01L23/538

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20240312957A1

公开(公告)日：2024-09-19

申请号：US18399504

申请日：2023-12-28

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/08 ,  H01L21/78 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06586 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/3025

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.