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    Three dimensional circuit implementing machine trained network
    3.
    发明授权
    Three dimensional circuit implementing machine trained network 有权

    公开(公告)号：US12248869B2

    公开(公告)日：2025-03-11

    申请号：US18469910

    申请日：2023-09-19

    Applicant: Adeia Semiconductor Inc.

    Inventor： Steven L. Teig ,  Kenneth Duong

    IPC: G06N3/065 ,  G06F11/14 ,  G06F11/20 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065 ,  H01L23/00 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H03K19/21

    Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

    Stacked IC structure with orthogonal interconnect layers
    4.
    发明授权
    Stacked IC structure with orthogonal interconnect layers 有权

    公开(公告)号：US11881454B2

    公开(公告)日：2024-01-23

    申请号：US17201732

    申请日：2021-03-15

    Applicant: ADEIA SEMICONDUCTOR INC.

    Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. Delacruz

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L21/822 ,  H01L27/06 ,  H01L23/522 ,  H01L25/065

    CPC classification number: H01L23/5286 ,  H01L21/8221 ,  H01L23/50 ,  H01L23/5225 ,  H01L24/26 ,  H01L25/0657 ,  H01L27/0688 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08147 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/15311

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK
    6.
    发明申请
    3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK 有权

    公开(公告)号：US20230137580A1

    公开(公告)日：2023-05-04

    申请号：US18146709

    申请日：2022-12-27

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

    IPC: H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    3D chip with shared clock distribution network
    7.
    发明授权
    3D chip with shared clock distribution network 有权

    公开(公告)号：US11557516B2

    公开(公告)日：2023-01-17

    申请号：US16953113

    申请日：2020-11-19

    Applicant: ADEIA SEMICONDUCTOR INC.

    Inventor： Javier DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

    IPC: H01L23/02 ,  H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK
    8.
    发明申请
    3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK 有权

    公开(公告)号：US20250142942A1

    公开(公告)日：2025-05-01

    申请号：US18906050

    申请日：2024-10-03

    Applicant: Adeia Semiconductor Inc.

    Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

    IPC: H10D84/03 ,  H01L21/768 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L25/065 ,  H10D88/00

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

    Stacked IC structure with orthogonal interconnect layers
    10.
    发明授权
    Stacked IC structure with orthogonal interconnect layers 有权

    公开(公告)号：US12218059B2

    公开(公告)日：2025-02-04

    申请号：US18399485

    申请日：2023-12-28

    Applicant: Adeia Semiconductor Inc.

    Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. DeLaCruz

    IPC: H01L23/528 ,  H01L21/822 ,  H01L23/00 ,  H01L23/50 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

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