公开(公告)号：US12293993B2

公开(公告)日：2025-05-06

申请号：US18379925

申请日：2023-10-13

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L21/822 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/60 ,  H01L25/00 ,  H01L27/06 ,  H01L23/50

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US12142528B2

公开(公告)日：2024-11-12

申请号：US18146709

申请日：2022-12-27

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US20240234320A1

公开(公告)日：2024-07-11

申请号：US18399485

申请日：2023-12-28

Applicant: Adeia Semiconductor Inc.

Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. DeLaCruz

IPC: H01L23/528 ,  H01L21/822 ,  H01L23/00 ,  H01L23/50 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/8221 ,  H01L23/50 ,  H01L23/5225 ,  H01L24/26 ,  H01L25/0657 ,  H01L27/0688 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08147 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/15311

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US11824042B2

公开(公告)日：2023-11-21

申请号：US17105272

申请日：2020-11-25

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/822 ,  H01L25/00 ,  H01L23/498 ,  H01L23/60 ,  H01L23/522 ,  H01L27/06 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L21/8221 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/60 ,  H01L24/32 ,  H01L25/50 ,  H01L27/0688 ,  H01L23/50 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05571 ,  H01L2224/08147 ,  H01L2224/09181 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US11515291B2

公开(公告)日：2022-11-29

申请号：US16397202

申请日：2019-04-29

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier A. Delacruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20250142942A1

公开(公告)日：2025-05-01

申请号：US18906050

申请日：2024-10-03

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H10D84/03 ,  H01L21/768 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L25/065 ,  H10D88/00

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US20240345399A1

公开(公告)日：2024-10-17

申请号：US18408074

申请日：2024-01-09

Applicant: Adeia Semiconductor Inc.

Inventor： Ilyas Mohammed ,  Rajesh Katkar ,  Belgacem Haba

IPC: G02B27/01 ,  G02B27/14

CPC classification number: G02B27/0172 ,  G02B6/0035 ,  G02B6/0076 ,  G02B27/144 ,  G02B2027/0178

Abstract: An optical apparatus is provided comprising: first and second optical waveguides disposed in a substrate such that light reflected by a beam splitting optical element of the first waveguide passes between beam splitting elements of the second waveguide.

公开(公告)号：US11894345B2

公开(公告)日：2024-02-06

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/522 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L23/552 ,  H01L24/08 ,  H01L21/78 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06586 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/3025

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US20230090121A1

公开(公告)日：2023-03-23

申请号：US18058677

申请日：2022-11-23

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Don Draper ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552

Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

公开(公告)号：US11881454B2

公开(公告)日：2024-01-23

申请号：US17201732

申请日：2021-03-15

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Ilyas Mohammed ,  Steven L. Teig ,  Javier A. Delacruz

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/50 ,  H01L21/822 ,  H01L27/06 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/5286 ,  H01L21/8221 ,  H01L23/50 ,  H01L23/5225 ,  H01L24/26 ,  H01L25/0657 ,  H01L27/0688 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08147 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/15311

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.