公开(公告)号：US20210193515A1

公开(公告)日：2021-06-24

申请号：US17110709

申请日：2020-12-03

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Shinya Iwashita ,  Jan Willem Maes ,  Jiyeon Kim

IPC: H01L21/768 ,  H01L21/67 ,  C23C16/52 ,  C23C16/455 ,  C23C16/34 ,  C23C16/06 ,  C23C16/46

Abstract: Systems and methods are described for depositing a TiN liner layer and a cobalt seed layer on a semiconductor wafer in a cobalt metallization process. In some embodiments the wafer is cooled after deposition of the TiN liner layer and/or the cobalt seed layer. In some embodiments the TiN liner layer and cobalt seed layer are deposited in process modules that are part of a semiconductor processing apparatus that also includes one or more modules for cooling the substrate. In some embodiments the cobalt seed layer may comprise a mixture of TiN and cobalt, a nanolaminate of TiN and cobalt layers or a graded TiN/Co layer.

公开(公告)号：US20200343358A1

公开(公告)日：2020-10-29

申请号：US16924595

申请日：2020-07-09

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/455 ,  H01L29/49 ,  C23C16/34

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

公开(公告)号：US10607895B2

公开(公告)日：2020-03-31

申请号：US15707786

申请日：2017-09-18

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Chiyu Zhu ,  Kiran Shrestha ,  Pauline Calka ,  Oreste Madia ,  Jan Willem Maes ,  Michael Eugene Givens

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092

Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.

公开(公告)号：US20190249312A1

公开(公告)日：2019-08-15

申请号：US16390385

申请日：2019-04-22

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi P. Haukka ,  Marko J. Tuominen ,  Chiyu Zhu

IPC: C23F4/02 ,  H01L21/3213 ,  C23F1/12 ,  C09K13/00 ,  C09K13/10 ,  H01L21/311 ,  H01L21/3065 ,  C09K13/08 ,  H01J37/32

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

公开(公告)号：US20190242019A1

公开(公告)日：2019-08-08

申请号：US16390540

申请日：2019-04-22

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi Haukka ,  Marko Tuominen ,  Chiyu Zhu

IPC: C23F4/02 ,  H01J37/32 ,  H01L21/3213 ,  H01L21/311 ,  C09K13/00 ,  H01L21/3065 ,  C23F1/12

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

公开(公告)号：US20190153593A1

公开(公告)日：2019-05-23

申请号：US16258187

申请日：2019-01-25

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Suvi Haukka

IPC: C23C16/38 ,  C23C16/455

Abstract: A method for depositing a metal film onto a substrate is disclosed. In particular, the method comprises pulsing a metal halide precursor onto the substrate and pulsing a decaborane precursor onto the substrate. A reaction between the metal halide precursor and the decaborane precursor forms a metal film, specifically a metal boride.

公开(公告)号：US20190140067A1

公开(公告)日：2019-05-09

申请号：US16240392

申请日：2019-01-04

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Timo Asikainen ,  Robert Brennan Milligan

IPC: H01L29/49 ,  C23C16/32 ,  H01L21/28 ,  C23C16/455 ,  H01L21/02 ,  C23C16/04 ,  H01L21/3205 ,  H01L21/285

Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.

公开(公告)号：US20180163312A1

公开(公告)日：2018-06-14

申请号：US15835262

申请日：2017-12-07

Applicant: ASM IP Holding B.V.

Inventor： Tom E. Blomberg ,  Varun Sharma ,  Suvi Haukka ,  Marko Tuominen ,  Chiyu Zhu

IPC: C23F4/02 ,  C23F1/12 ,  C09K13/00

CPC classification number: C23F4/02 ,  C09K13/00 ,  C23F1/12 ,  H01J37/32009 ,  H01J37/3244 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/32135

Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

公开(公告)号：US20180012792A1

公开(公告)日：2018-01-11

申请号：US15205890

申请日：2016-07-08

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/76832

Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

公开(公告)号：US20250081588A1

公开(公告)日：2025-03-06

申请号：US18950377

申请日：2024-11-18

Applicant: ASM IP Holding B.V.

Inventor： Chiyu Zhu ,  Kiran Shrestha ,  Petri Raisanen ,  Michael Eugene Givens

IPC: H01L29/51 ,  C23C16/34 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

Abstract: Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.