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    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    12.
    发明公开
    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240030120A1

    公开(公告)日：2024-01-25

    申请号：US18375140

    申请日：2023-09-29

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L23/3157 ,  H01L21/4857 ,  H01L23/49816 ,  H01L21/486 ,  H01L23/49822

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

    SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    14.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210210446A1

    公开(公告)日：2021-07-08

    申请号：US16735002

    申请日：2020-01-06

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/00

    Abstract: A semiconductor device package includes a redistribution structure and an electrical connection. The redistribution structure has an electrical terminal adjacent to a surface of the redistribution structure and a seed layer covering a side surface of the electrical terminal. The electrical connection is disposed on a first surface of the electrical terminal. The seed layer extends to the first surface of the electrical terminal.

    SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR MANUFACTURING PROCESS
    15.
    发明申请
    SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR MANUFACTURING PROCESS 审中-公开

    公开(公告)号：US20200258826A1

    公开(公告)日：2020-08-13

    申请号：US16859676

    申请日：2020-04-27

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Li-Chuan TSAI

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/16 ,  H01L21/683

    Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

    SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190148297A1

    公开(公告)日：2019-05-16

    申请号：US15815351

    申请日：2017-11-16

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chung Chieh CHANG ,  Ya Fang CHAN ,  Chih-Cheng LEE

    IPC: H01L23/535 ,  H01L21/02

    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another. The second central axes of the first and second conductive elements are substantially co-linear in the second direction. The second central axis of the third conductive element is substantially parallel to and misaligned from the second central axes of the first and second conductive elements. The first chamfer and the second chamfer are separated by at least one of the first central axis and the second central axis of the first conductive element and are substantially asymmetric.

    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS
    17.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS 有权
    半导体封装结构与半导体工艺

    公开(公告)号：US20160143149A1

    公开(公告)日：2016-05-19

    申请号：US14548118

    申请日：2014-11-19

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Yuan-Chang SU ,  Chih-Cheng LEE ,  Cheng-Lin HO

    IPC: H05K1/18 ,  H01L21/48 ,  H05K3/18 ,  H05K3/46 ,  H05K3/10 ,  H01L23/498 ,  H05K3/30

    CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/188 ,  H01L2924/00

    Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

    Abstract translation: 公开了半导体封装结构和制造方法。 半导体封装结构包括第一电介质层，第二电介质层，部件，图案化导电层和至少两个导电通孔。 第一电介质层具有与第一表面相对的第一表面和第二表面。 第二电介质层具有与第一表面相对的第一表面和第二表面。 第一电介质层的第二表面附着到第二电介质层的第一表面。 第二电介质层内的部件具有与第一电介质层的第二表面相邻的至少两个电触点。 第一介电层内的图案化导电层与第一介电层的第一表面相邻。 导电通孔穿透第一电介质层并将电触点与图案化的导电层电连接。

    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    18.
    发明申请
    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210366816A1

    公开(公告)日：2021-11-25

    申请号：US17397842

    申请日：2021-08-09

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    20.
    发明申请
    SUBSTRATE, SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200211948A1

    公开(公告)日：2020-07-02

    申请号：US16814729

    申请日：2020-03-10

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

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