SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE STRUCTURE

    公开(公告)号:US20210013118A1

    公开(公告)日:2021-01-14

    申请号:US16508210

    申请日:2019-07-10

    Abstract: A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device.

    Power and ground design for through-silicon via structure

    公开(公告)号:US10600759B2

    公开(公告)日:2020-03-24

    申请号:US15404093

    申请日:2017-01-11

    Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.

    Wiring structure
    17.
    发明授权

    公开(公告)号:US11227823B2

    公开(公告)日:2022-01-18

    申请号:US16853396

    申请日:2020-04-20

    Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.

    Electronic device package and method for manufacturing the same

    公开(公告)号:US11183474B2

    公开(公告)日:2021-11-23

    申请号:US16673699

    申请日:2019-11-04

    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

    Semiconductor devices and semiconductor packages

    公开(公告)号:US10658319B2

    公开(公告)日:2020-05-19

    申请号:US16247437

    申请日:2019-01-14

    Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

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