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公开(公告)号:US11075186B2
公开(公告)日:2021-07-27
申请号:US15429024
申请日:2017-02-09
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Ian Hu , Jia-Rung Ho , Jin-Feng Yang , Chih-Pin Hung , Ping-Feng Yang
IPC: H01L23/00 , H01L23/367 , H01L23/31 , H01L23/04 , H01L23/373
Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.
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公开(公告)号:US20210013118A1
公开(公告)日:2021-01-14
申请号:US16508210
申请日:2019-07-10
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Hsin-En Chen , Ian Hu , Chih-Pin Hung
IPC: H01L23/367 , H01L23/427
Abstract: A semiconductor package structure includes a package substrate, at least one semiconductor die, a heat dissipating device, at least one electronic device and a heat transmitting structure. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is electrically connected to the first surface of the package substrate. The heat dissipating device is thermally connected to the first surface of the package substrate. The electronic device is electrically connected to the second surface of the package substrate. The electronic device has a first surface and a second surface opposite to the first surface, and the first surface of the electronic device faces the second surface of the package substrate. The heat transmitting structure is disposed adjacent to the second surface of the package substrate, and thermally connected to the electronic device and the heat dissipating device.
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公开(公告)号:US10600759B2
公开(公告)日:2020-03-24
申请号:US15404093
申请日:2017-01-11
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chih-Pin Hung , Ying-Te Ou , Pao-Nan Lee
IPC: H01L25/065 , H01L23/522 , H01L23/528 , H01L25/00 , H01L23/31
Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.
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公开(公告)号:US10217649B2
公开(公告)日:2019-02-26
申请号:US15619415
申请日:2017-06-09
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Jin-Yuan Lai , Tang-Yuan Chen , Ying-Xu Lu , Dao-Long Chen , Kwang-Lung Lin , Chih-Pin Hung , Tse-Chuan Chou , Ming-Hung Chen , Chi-Hung Pan
IPC: H01L23/49 , H01L21/56 , H01L23/00 , H01L21/48 , H01L23/498
Abstract: A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.
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公开(公告)号:US11837566B2
公开(公告)日:2023-12-05
申请号:US17534358
申请日:2021-11-23
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Mei-Ju Lu , Chi-Han Chen , Chang-Yu Lin , Jr-Wei Lin , Chih-Pin Hung
IPC: H01L23/00
CPC classification number: H01L24/17 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L2224/02373 , H01L2224/02375 , H01L2224/02377 , H01L2224/02381 , H01L2224/13024 , H01L2224/13082 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/17177 , H01L2224/73204 , H01L2224/81951
Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
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公开(公告)号:US11777191B2
公开(公告)日:2023-10-03
申请号:US17133369
申请日:2020-12-23
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Cheng-Yu Ho , Sheng-Chi Hsieh , Chih-Pin Hung
CPC classification number: H01Q1/2283 , H01L23/66 , H01Q1/523 , H01Q25/005 , H01L2223/6677
Abstract: The present disclosure relates to a wireless communication module. The wireless communication module includes a first antenna layer and a second antenna layer non-coplanar with the second antenna layer. An electromagnetic wave of the first antenna and the second antenna are configured to have far-field interference to each other.
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公开(公告)号:US11227823B2
公开(公告)日:2022-01-18
申请号:US16853396
申请日:2020-04-20
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Tang-Yuan Chen , Chih-Pin Hung
IPC: H05K1/11 , H05K1/14 , H01L23/498 , H01L23/00 , H01L23/538 , H05K1/02
Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.
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公开(公告)号:US11183474B2
公开(公告)日:2021-11-23
申请号:US16673699
申请日:2019-11-04
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Mei-Ju Lu , Chi-Han Chen , Chang-Yu Lin , Jr-Wei Lin , Chih-Pin Hung
IPC: H01L23/00
Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
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公开(公告)号:US10886263B2
公开(公告)日:2021-01-05
申请号:US15721257
申请日:2017-09-29
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: William T. Chen , John Richard Hunt , Chih-Pin Hung , Chen-Chao Wang , Chih-Yi Huang
IPC: H01L25/10 , H01L23/538 , H01L23/31 , H01L23/367 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L25/00 , H01L25/16 , H01L25/18 , H01L23/13 , H01L25/07 , H01L25/075 , H01L25/11 , H01L25/04 , H01L25/065
Abstract: A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.
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公开(公告)号:US10658319B2
公开(公告)日:2020-05-19
申请号:US16247437
申请日:2019-01-14
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor: Chih-Pin Hung , Dao-Long Chen , Ying-Ta Chiu , Ping-Feng Yang
IPC: H01L23/00
Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.
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