公开(公告)号：US09911702B2

公开(公告)日：2018-03-06

申请号：US14268981

申请日：2014-05-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US11835363B2

公开(公告)日：2023-12-05

申请号：US17684374

申请日：2022-03-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chung Chen ,  Hsun-Wei Chan ,  Lu-Ming Lai ,  Kuang-Hsiung Chen

IPC: G01C3/08

CPC classification number: G01C3/08

Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

公开(公告)号：US10049976B2

公开(公告)日：2018-08-14

申请号：US15006306

申请日：2016-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.

公开(公告)号：US20160079194A1

公开(公告)日：2016-03-17

申请号：US14855849

申请日：2015-09-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.

Abstract translation: 半导体衬底包括绝缘层，邻近绝缘层的第一表面设置的第一导电图案层和设置在第一导电图案层上的导电凸块。 每个导电凸块具有沿着第一方向的第一尺寸和沿着垂直于第一方向的第二方向的第二尺寸，并且第一尺寸大于第二尺寸。 半导体封装结构包括半导体衬底，至少一个与导电凸块电连接的管芯，以及封装导电凸块的模制化合物。

公开(公告)号：US09165900B2

公开(公告)日：2015-10-20

申请号：US14174364

申请日：2014-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Chia-Hsiung Hsieh ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H05K1/11

CPC classification number: H01L23/3128 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/27013 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) a patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

Abstract translation: 包装载体包括：（a）限定多个开口的电介质层; （b）图案化的导电层，嵌入在介电层中并邻近电介质层的第一表面设置; （c）多个导电柱，设置在各个开口中，其中开口在介质层的第二表面与图案化的导电层之间延伸，导电柱连接到图案化的导电层， 并且每个导电柱的端部具有弯曲轮廓并且背离图案化的导电层; 和（d）图案化的阻焊层，邻近电介质层的第一表面设置并暴露与接触焊盘对应的图案化导电层的部分。 半导体封装包括封装载体，芯片和覆盖芯片和封装载体的密封剂。

公开(公告)号：US20140346670A1

公开(公告)日：2014-11-27

申请号：US14453139

申请日：2014-08-06

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/00 ,  H01L23/28

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

公开(公告)号：US08884424B2

公开(公告)日：2014-11-11

申请号：US14033673

申请日：2013-09-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/12 ,  H01L23/053 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Abstract translation: 多层衬底包括第一外部导电图案化层，暴露第一外部导电图案化层的一部分以限定第一组焊盘的第一绝缘层，第二外部导电图案化层和暴露部分第一绝缘层的第二绝缘层 第二外导电图案层以限定第二组焊盘。 多层基板还包括内层，每层具有内部导电图案层，邻近内部导电图案化层形成的多个内部导电柱和内部电介质层，其中内部导电图案层和内部导电柱嵌入内部 电介质层和每个内部导电柱的顶表面从内部电介质层露出。

公开(公告)号：US20140084475A1

公开(公告)日：2014-03-27

申请号：US13624548

申请日：2012-09-21

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。

公开(公告)号：US11631633B2

公开(公告)日：2023-04-18

申请号：US17204833

申请日：2021-03-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Kuang-Hsiung Chen ,  Bernd Karl Appelt

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/768 ,  H01L21/50

Abstract: A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.

公开(公告)号：US10734337B2

公开(公告)日：2020-08-04

申请号：US16293606

申请日：2019-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung Chen ,  Yu-Hsuan Tsai ,  Yu-Ying Lee ,  Sheng-Ming Wang ,  Wun-Jheng Syu

IPC: H01L23/28 ,  H01L23/00 ,  B81C1/00 ,  B81B7/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.