公开(公告)号：US20190148280A1

公开(公告)日：2019-05-16

申请号：US16247441

申请日：2019-01-14

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chun-Che Lee ,  Ming-Chiang Lee ,  Yuan-Chang Su ,  Tien-Szu Chen ,  Chih-Cheng Lee ,  You-Lung Yen

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US10049976B2

公开(公告)日：2018-08-14

申请号：US15006306

申请日：2016-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.

公开(公告)号：US20160079194A1

公开(公告)日：2016-03-17

申请号：US14855849

申请日：2015-09-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.

Abstract translation: 半导体衬底包括绝缘层，邻近绝缘层的第一表面设置的第一导电图案层和设置在第一导电图案层上的导电凸块。 每个导电凸块具有沿着第一方向的第一尺寸和沿着垂直于第一方向的第二方向的第二尺寸，并且第一尺寸大于第二尺寸。 半导体封装结构包括半导体衬底，至少一个与导电凸块电连接的管芯，以及封装导电凸块的模制化合物。

公开(公告)号：US20140084475A1

公开(公告)日：2014-03-27

申请号：US13624548

申请日：2012-09-21

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。

公开(公告)号：US10446411B2

公开(公告)日：2019-10-15

申请号：US16102527

申请日：2018-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Yu-Tzu Peng

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31 ,  H05K1/14 ,  H05K3/28 ,  H01L23/538

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

公开(公告)号：US10103110B2

公开(公告)日：2018-10-16

申请号：US15873784

申请日：2018-01-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US20160104667A1

公开(公告)日：2016-04-14

申请号：US14971165

申请日：2015-12-16

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L23/498 ,  H01L21/027 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

公开(公告)号：US08884443B2

公开(公告)日：2014-11-11

申请号：US13895704

申请日：2013-05-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Chun-Che Lee ,  Sheng-Ming Wang

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/0273 ,  H01L21/48 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/768 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Abstract translation: 半导体封装基板包括芯部，上电路层和多个支柱。 支柱设置在上电路层上并从上电路层向上突出。 支柱的顶面基本上共面。 支柱提供与半导体管芯的电互连。 提高了基板与半导体管芯之间的焊接可靠性。

公开(公告)号：US11894308B2

公开(公告)日：2024-02-06

申请号：US17109111

申请日：2020-12-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming Wang ,  Tien-Szu Chen ,  Wen-Chih Shen ,  Hsing-Wen Lee ,  Hsiang-Ming Feng

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/66 ,  H01L23/367 ,  H01P3/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/5383 ,  H01L23/66 ,  H01P3/06 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

公开(公告)号：US10181438B2

公开(公告)日：2019-01-15

申请号：US14523733

申请日：2014-10-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chun-Che Lee ,  Ming-Chiang Lee ,  Yuan-Chang Su ,  Tien-Szu Chen ,  Chih-Cheng Lee ,  You-Lung Yen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H01L21/48 ,  H05K3/46

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.