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    Integrated circuits with improved register circuitry
    11.
    发明授权
    Integrated circuits with improved register circuitry 有权

    公开(公告)号：US09660650B1

    公开(公告)日：2017-05-23

    申请号：US14209503

    申请日：2014-03-13

    Applicant: Altera Corporation

    Inventor： Valavan Manohararajah ,  Jeffrey Christopher Chromczak ,  David Lewis

    IPC: H03K19/173 ,  H03K19/0175 ,  G06F17/50

    CPC classification number: H03K19/017581 ,  G06F17/505 ,  H03K19/17728 ,  H03K19/17744

    Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations within a design while ensuring correct clock enable functionality. A group of programmable logic regions may have shared input selection circuitry that selects register control signals and produces delayed versions of the signals that are shared by the group. If desired, each programmable logic region may be provided with adjustable delay circuitry that individually adjusts control signal delay for registers of that programmable logic region.

    Error detection and correction circuitry
    12.
    发明授权
    Error detection and correction circuitry 有权

    公开(公告)号：US09600366B1

    公开(公告)日：2017-03-21

    申请号：US14632461

    申请日：2015-02-26

    Applicant: Altera Corporation

    Inventor： Paul B. Ekas ,  David Lewis

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/10 ,  G06F11/1048 ,  G11C11/412 ,  G11C29/52 ,  G11C2029/0411 ,  H03K19/17768

    Abstract: Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

    Methods and apparatus for detecting memory bit corruption on an integrated circuit
    13.
    发明授权
    Methods and apparatus for detecting memory bit corruption on an integrated circuit 有权
    用于检测集成电路上的存储器位损坏的方法和装置

    公开(公告)号：US09582349B1

    公开(公告)日：2017-02-28

    申请号：US14464244

    申请日：2014-08-20

    Applicant: Altera Corporation

    Inventor： Herman Henry Schmit ,  David Lewis

    IPC: G06F11/07 ,  G06F11/22

    CPC classification number: G06F11/0763 ,  G06F11/073 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/5006

    Abstract: An integrated circuit may have a memory bit corruption detection circuit. The memory bit corruption detection circuit may monitor a circuit that stores multiple data bits using a current sensing circuit and a fault detection circuit. When a bit of the data bits gets corrupted, a current may flow through a predetermined node in the monitored circuit which may be sensed by the current sensing circuit. The current may have a particular current profile that may be distinguishable from current flows that occur during normal operation of the monitored circuit. The fault detection circuit may recognize the particular current profile that is indicative of a corrupted memory bit in the monitored circuit and generate a fault signal to indicate that memory bit corruption has occurred in the monitored circuit.

    Abstract translation: 集成电路可能具有存储器位坏损检测电路。 存储器位故障检测电路可以使用电流检测电路和故障检测电路监视存储多个数据位的电路。 当一位数据位被破坏时，电流可能流过被监测电路中的预定节点，该电流可由电流感测电路感测。 电流可以具有可以与在监视电路的正常操作期间发生的电流流动区分开的特定电流分布。 故障检测电路可以识别指示所监视的电路中的损坏的存储器位的特定电流分布，并产生故障信号以指示所监视的电路中已经发生存储器位损坏。

    Clocking for pipelined routing
    15.
    发明授权
    Clocking for pipelined routing 有权
    时钟流水线路由

    公开(公告)号：US09360884B2

    公开(公告)日：2016-06-07

    申请号：US14075802

    申请日：2013-11-08

    Applicant: Altera Corporation

    Inventor： David Galloway ,  David Lewis ,  Ryan Fung ,  Valavan Manohararajah ,  Jeffrey Christopher Chromczak

    IPC: G06F13/34 ,  G06F1/10 ,  G06F1/08

    CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F13/4068

    Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

    Abstract translation: 集成电路可以具有流水线可编程互连，其被配置为在存储在寄存器中的路由信号与绕过寄存器的相同路由信号之间进行选择。 流水线可编程互连可以通过线将所选择的路由信号发送到下一个流水线可编程互连电路。 集成电路还可以具有时钟路由选择电路，以选择用于不同流水线可编程互连中的寄存器的相应时钟信号。 时钟路由电路可以包括传送区域时钟的第一互连，传送路由时钟的第二互连，第一选择器电路，以选择区域时钟之间的路由时钟;以及第二选择器电路，以选择各个寄存器的路由时钟。

    Memory error detection circuitry
    16.
    发明授权
    Memory error detection circuitry 有权

    公开(公告)号：US09336078B1

    公开(公告)日：2016-05-10

    申请号：US14052472

    申请日：2013-10-11

    Applicant: Altera Corporation

    Inventor： Kostas Pagiamtzis ,  David Lewis

    IPC: H03M13/00 ,  G06F11/10

    CPC classification number: G06F11/10 ,  G06F11/1048

    Abstract: Integrated circuits with memory elements may be provided. Integrated circuits may include memory error detection circuitry that is capable of correcting single-bit errors, correcting adjacent double-bit errors, and detecting adjacent triple-bit errors. The memory error detection circuitry may include encoding circuitry that generates parity check bits interleaved among memory data bits. The memory error detection circuitry may include decoding circuitry that is used to generate output data and error signals to indicate whether a correctable soft error or an uncorrectable soft error has been detected. The output data may be written back to the memory elements if a correctable soft error is detected. The memory error detection circuitry may be operable in a pipelined or a non-pipelined mode depending on the desired application.

    Apparatus for Using Metastability-Hardened Storage Circuits in Logic Devices and Associated Methods
    20.
    发明申请
    Apparatus for Using Metastability-Hardened Storage Circuits in Logic Devices and Associated Methods 审中-公开
    在逻辑器件中使用转移性硬化存储电路的装置及相关方法

    公开(公告)号：US20130328607A1

    公开(公告)日：2013-12-12

    申请号：US13964901

    申请日：2013-08-12

    Applicant: Altera Corporation

    Inventor： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

    IPC: H03K3/356

    CPC classification number: H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

    Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

    Abstract translation: 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

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