公开(公告)号：US09593991B2

公开(公告)日：2017-03-14

申请号：US14812958

申请日：2015-07-29

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Bryan McDonald ,  Shawn X. Arnold ,  Matthew Casebolt ,  Dennis R. Pyper

IPC: G01L1/22 ,  G01L3/14

CPC classification number: G01L1/22 ,  G01L1/2262 ,  G01L1/2287 ,  G01L3/1457 ,  G01L5/0047 ,  G01M5/0033 ,  G01M5/0083

Abstract: A printed circuit board may have embedded strain gauges. A strain gauge may be formed from a metal trace on a polymer substrate. The metal trace may form a variable strain gauge resistor that is incorporated into a bridge circuit for a strain gauge. The printed circuit may have a rigid printed circuit layer with a recess that receives the polymer substrate. Metal pads on the polymer substrate may be coupled to respective ends of the variable strain gauge resistor. The rigid printed circuit substrate with the recess may be laminated between additional rigid printed circuit layers. Vias may be formed through the additional rigid printed circuit layers to contact the metal pads. Embedded strain gauges may be used in gathering strain data when strain is imparted to a printed circuit during use of the printed circuit in an electronic device or during testing.

Abstract translation: 印刷电路板可以具有嵌入式应变计。 应变计可由聚合物基底上的金属迹线形成。 金属痕迹可以形成可变应变计电阻器，其被并入用于应变仪的桥式电路中。 印刷电路可以具有刚性印刷电路层，其具有容纳聚合物基底的凹部。 聚合物基板上的金属焊盘可以连接到可变应变计电阻器的相应末端。 具有凹槽的刚性印刷电路基板可以层压在附加的刚性印刷电路层之间。 可以通过附加的刚性印刷电路层形成通孔以接触金属焊盘。 当在电子设备中使用印刷电路或在测试期间使用印刷电路时，嵌入式应变计可用于收集应变数据。

公开(公告)号：US10420213B2

公开(公告)日：2019-09-17

申请号：US15696102

申请日：2017-09-05

Applicant: Apple Inc.

Inventor： Mark J. Beesley ,  Albert A. Onderick, II ,  Anne M. Mason ,  Craig A. Gammel ,  Shawn X. Arnold

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K1/14

Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.

公开(公告)号：US09812401B2

公开(公告)日：2017-11-07

申请号：US15246481

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Peter J. Johnston ,  Christine A. Laliberte ,  Dominic P. McCarthy ,  Shawn X. Arnold ,  Souvik Mukherjee

IPC: H05K7/00 ,  H01L23/538 ,  H05K1/18 ,  H05K1/11 ,  H05K1/16 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01C7/00 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1434 ,  H01L2924/19043 ,  H05K1/113 ,  H05K1/167 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/4076 ,  H05K2201/096 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads. The interposer further including isolation resistors embedded within the first array of conductive vias, each isolation resistor being configured to produce a copy of a signal flowing through the conductive via that is coupled to one end of the isolation resistor on the conductive trace that is coupled to an opposite end of the isolation resistor.

公开(公告)号：US20170265304A1

公开(公告)日：2017-09-14

申请号：US15068474

申请日：2016-03-11

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Peter J. Johnston ,  Christine A. Laliberte ,  Dominic P. McCarthy ,  Shawn X. Arnold ,  Souvik Mukherjee

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/40 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01L23/5386 ,  H01C7/00 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/1434 ,  H01L2924/19043 ,  H05K1/113 ,  H05K1/167 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/4076 ,  H05K2201/096 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

公开(公告)号：US20150364255A1

公开(公告)日：2015-12-17

申请号：US14500786

申请日：2014-09-29

Applicant: Apple Inc.

Inventor： Gang Ning ,  Pradeep Vengavasi ,  Linda Y. Dunn ,  Yonas A. Hartanto ,  Shawn X. Arnold

IPC: H01G2/22 ,  H01G4/30 ,  H01G2/06 ,  H01G4/12

CPC classification number: H01G2/22 ,  H01G2/065 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: This disclosure describes methods and systems for minimizing electromagnetic interference (EMI) noise emanating from a ceramic capacitor. The ceramic capacitor may include several terminations are on a bottom portion of the capacitor. The capacitor may be designed to include several capacitors formed from electrode layers. The capacitor may include a conductive coating on an outer peripheral portion. The coating may include conductive materials such as Cu, Ni, Ag, and/or graphite. Alternatively, some regions of the capacitor may include electrode layers built into the capacitor that are not associated with capacitors. In this manner, the ceramic capacitor may be free of the conductive coating to locations proximate to the described electrode layers not associated with capacitors. The conductive coating can act as an electromagnetic shielding to prevent the EMI noise from emanating outside the electromagnetic shielding. Also, the conductive coating can be electrically grounded (e.g., to printed circuit board) via terminals.

Abstract translation: 本公开描述了用于最小化从陶瓷电容器发出的电磁干扰（EMI）噪声的方法和系统。 陶瓷电容器可以包括位于电容器底部的多个端子。 电容器可以被设计成包括由电极层形成的多个电容器。 电容器可以包括外周部分上的导电涂层。 涂层可以包括诸如Cu，Ni，Ag和/或石墨的导电材料。 或者，电容器的一些区域可以包括内置于不与电容器相关联的电容器中的电极层。 以这种方式，陶瓷电容器可以没有导电涂层到靠近所描述的与电容器不相关的电极层的位置。 导电涂层可以作为电磁屏蔽，以防止EMI噪声发散在电磁屏蔽外。 此外，导电涂层可以通过端子电接地（例如，到印刷电路板）。

公开(公告)号：US08664656B1

公开(公告)日：2014-03-04

申请号：US13644280

申请日：2012-10-04

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Dennis Pyper

IPC: H01L23/58 ,  H01L27/15 ,  H01L29/84 ,  H01L23/48

CPC classification number: H01L22/10 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/58 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L29/84 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/82138 ,  H05K1/00 ,  H05K1/0268 ,  H05K1/186 ,  H05K3/4611 ,  H05K2201/10674 ,  H05K2203/063

Abstract: Methods and devices for embedding semiconductors in printed circuit boards (PCBs) are provided. In one example, a method of manufacturing a PCB having a die assembly embedded therein includes removing a release film from an adhesive layer of the die assembly. The method also includes disposing the die assembly on a first layer of the PCB such that the adhesive layer contacts the first layer of the PCB. The method includes disposing a second layer of the PCB over the first layer such that the die assembly is within an intermediate portion between the first layer and the second layer. The method also includes filling the intermediate portion with resin and subjecting the PCB to a press cycle to cure the resin.

公开(公告)号：US10932366B2

公开(公告)日：2021-02-23

申请号：US15942970

申请日：2018-04-02

Applicant: Apple Inc.

Inventor： Sunil M. Akre ,  Shawn X. Arnold

IPC: H05K3/30 ,  H05K1/14 ,  H05K1/16 ,  H05K1/18

Abstract: Embedded PCB (printed circuit board) is used for the packaging and assembly of a low profile power conversion system module that can be employed in space constrained environment of small computer/electronic systems. The low profile power conversion system module may include an embedded PCB, a power silicon device embedded within the PCB, a magnetic component which is either embedded within the PCB or disposed on the PCB, or input/output terminals disposed on the side of the embedded PCB. The embedded PCB and the magnetic component may be thin planar shaped to save vertical space. The low profile power conversion system module can be placed inside a cavity formed in the system PCB to save even more vertical space.

公开(公告)号：US20170030784A1

公开(公告)日：2017-02-02

申请号：US14812958

申请日：2015-07-29

Applicant: Apple Inc.

Inventor： Anne M. Mason ,  Bryan McDonald ,  Shawn X. Arnold ,  Matthew Casebolt ,  Dennis R. Pyper

IPC: G01L1/22

CPC classification number: G01L1/22 ,  G01L1/2262 ,  G01L1/2287 ,  G01L3/1457 ,  G01L5/0047 ,  G01M5/0033 ,  G01M5/0083

Abstract: A printed circuit board may have embedded strain gauges. A strain gauge may be formed from a metal trace on a polymer substrate. The metal trace may form a variable strain gauge resistor that is incorporated into a bridge circuit for a strain gauge. The printed circuit may have a rigid printed circuit layer with a recess that receives the polymer substrate. Metal pads on the polymer substrate may be coupled to respective ends of the variable strain gauge resistor. The rigid printed circuit substrate with the recess may be laminated between additional rigid printed circuit layers. Vias may be formed through the additional rigid printed circuit layers to contact the metal pads. Embedded strain gauges may be used in gathering strain data when strain is imparted to a printed circuit during use of the printed circuit in an electronic device or during testing.

Abstract translation: 印刷电路板可以具有嵌入式应变计。 应变计可由聚合物基底上的金属迹线形成。 金属痕迹可以形成可变应变计电阻器，其被并入用于应变仪的桥式电路中。 印刷电路可以具有刚性印刷电路层，其具有容纳聚合物基底的凹部。 聚合物基板上的金属焊盘可以连接到可变应变计电阻器的相应末端。 具有凹槽的刚性印刷电路基板可以层压在附加的刚性印刷电路层之间。 可以通过附加的刚性印刷电路层形成通孔以接触金属焊盘。 当在电子设备中使用印刷电路或在测试期间使用印刷电路时，嵌入式应变计可用于收集应变数据。

公开(公告)号：US09190379B2

公开(公告)日：2015-11-17

申请号：US13629544

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Matthew E. Last

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/19 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: One embodiment of a perimeter trench sensor array package can include a thinned substrate device that includes a perimeter trench formed near the edges of the device that can be configured to be thinner than a central portion of the thinned substrate device. The perimeter trench can include bond pads that can couple to electrical elements included in the thinned substrate device. The thinned substrate device can be attached to a core layer that can in turn support one or more resin layers. The core layer and the resin layers can form a printed circuit board assembly, a flex cable assembly or a stand-alone module.

Abstract translation: 周边沟槽传感器阵列封装的一个实施例可以包括减薄的衬底器件，其包括在器件边缘附近形成的周边沟槽，该周边沟槽可以被配置为比薄的衬底器件的中心部分更薄。 周边沟槽可以包括可以耦合到包括在薄化衬底器件中的电气元件的接合焊盘。 可以将薄化的衬底装置附接到可以依次支撑一个或多个树脂层的芯层。 芯层和树脂层可以形成印刷电路板组件，柔性电缆组件或独立模块。

公开(公告)号：US20150230339A1

公开(公告)日：2015-08-13

申请号：US14696327

申请日：2015-04-24

Applicant: Apple Inc.

Inventor： Shawn X. Arnold ,  Terry L. Gilton ,  Matthew E. Last

IPC: H05K1/18 ,  G06F1/16 ,  H05K1/11 ,  G06F3/041

CPC classification number: H05K1/183 ,  G06F1/16 ,  G06F3/041 ,  G06K9/00053 ,  H01L23/24 ,  H01L24/11 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48479 ,  H01L2224/85 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H05K1/111 ,  H05K2201/09036 ,  H05K2201/10151 ,  H01L2924/20752 ,  H01L2224/48471 ,  H01L2224/4554

Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.

Abstract translation: 描述了用于形成低轮廓组件的各种方法。 薄型组件可以包括集成电路。 集成电路以及与集成电路相关的部件可以位于集成电路所在的印刷电路板的表面的下方。 集成电路可以包括配置成将集成电路电连接到其他部件的接合线。 薄型组件可以包括在衬底上形成各种层并且随后去除一些层。