公开(公告)号：US11621393B2

公开(公告)日：2023-04-04

申请号：US17112484

申请日：2020-12-04

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala

IPC: H01L43/12 ,  C23C14/06 ,  C23C14/54 ,  H01F10/32 ,  H01F41/32 ,  H01L43/10 ,  H01L43/02 ,  H01F10/13 ,  H01L21/67 ,  C23C14/00 ,  H01F41/30 ,  H01F10/30 ,  G11C11/16

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US11374165B2

公开(公告)日：2022-06-28

申请号：US16810697

申请日：2020-03-05

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Sajjad Amin Hassan ,  Mahendra Pakala ,  Jaesoo Ahn

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a chemical mechanical polishing process to improve surface roughness. An magnetic tunnel junction deposition is then performed over the bottom electrode buff layer.

公开(公告)号：US11133460B2

公开(公告)日：2021-09-28

申请号：US15438420

申请日：2017-02-21

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Mahendra Pakala ,  Chi Hong Ching ,  Rongjun Wang

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/14 ,  H01F10/32

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

公开(公告)号：US11127760B2

公开(公告)日：2021-09-21

申请号：US16265192

申请日：2019-02-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Thomas Kwon ,  Mahendra Pakala

IPC: H01L29/66 ,  H01L27/11597 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US20240138147A1

公开(公告)日：2024-04-25

申请号：US18486576

申请日：2023-10-12

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Jose Alexandro Romero ,  Kunal Bhatnagar ,  Mahendra Pakala

IPC: H10B43/20 ,  H01L21/02

CPC classification number: H10B43/20 ,  H01L21/0228 ,  H10B43/35

Abstract: A method includes obtaining a base structure of a three-dimensional (3D) memory device, forming, on the base structure, a blocking layer including a high-k dielectric material, and forming, on the blocking layer, a wordline for the 3D memory device including molybdenum using an atomic layer deposition (ALD) process.

公开(公告)号：US11522126B2

公开(公告)日：2022-12-06

申请号：US16601250

申请日：2019-10-14

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Sahil Patel ,  Chando Park ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  G11B5/39 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

Abstract: A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

公开(公告)号：US10923652B2

公开(公告)日：2021-02-16

申请号：US16448709

申请日：2019-06-21

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  C23C14/54 ,  H01F10/32 ,  H01L43/10 ,  H01F41/32 ,  C23C14/06 ,  H01L21/67 ,  H01F10/13

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US10756259B2

公开(公告)日：2020-08-25

申请号：US16290621

申请日：2019-03-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Chando Park ,  Hsin-wei Tseng ,  Lin Xue ,  Mahendra Pakala

IPC: H01L27/00 ,  H01L43/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

公开(公告)号：US10586914B2

公开(公告)日：2020-03-10

申请号：US15712185

申请日：2017-09-22

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Sajjad Amin Hassan ,  Mahendra Pakala ,  Jaesoo Ahn

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.

公开(公告)号：US09991118B2

公开(公告)日：2018-06-05

申请号：US15398591

申请日：2017-01-04

Applicant: Applied Materials, Inc.

Inventor： Thomas Jongwan Kwon ,  Rui Cheng ,  Abhijit Basu Mallick ,  Er-Xuan Ping ,  Jaesoo Ahn

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/11582 ,  H01L49/02

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.